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VCVTNEPS2BF16
VCVTNEPS2BF16 — Convert Packed Single Data to Packed BF16 Data
| Opcode/ Instruction | Op/ En | 64/32 Bit Mode Support | CPUID Feature Flag | Description |
| VEX.128.F3.0F38.W0 72 /r VCVTNEPS2BF16 xmm1, xmm2/m128 | AV/V | AVX_NE_ CONVERT | Convert packed single precision floating-point values from xmm2/m128 to packed BF16 values and store in xmm1. | |
| VEX.256.F3.0F38.W0 72 /r VCVTNEPS2BF16 xmm1, ymm2/m256 | AV/V | AVX_NE_ CONVERT | Convert packed single precision floating-point values from ymm2/m256 to packed BF16 values and store in xmm1. | |
| EVEX.128.F3.0F38.W0 72 /r VCVTNEPS2BF16 xmm1{k1}{z}, xmm2/m128/m32bcst | B | V/V | (AVX512_BF16 AND AVX512VL) OR AVX10.1 | Convert packed single data from xmm2/m128 to packed BF16 data in xmm1 with writemask k1. |
| EVEX.256.F3.0F38.W0 72 /r VCVTNEPS2BF16 xmm1{k1}{z}, ymm2/m256/m32bcst | B | V/V | (AVX512_BF16 AND AVX512VL) OR AVX10.1 | Convert packed single data from ymm2/m256 to packed BF16 data in xmm1 with writemask k1. |
| EVEX.512.F3.0F38.W0 72 /r VCVTNEPS2BF16 ymm1{k1}{z}, zmm2/m512/m32bcst | B | V/V | (AVX512_BF16 AND AVX512F) OR AVX10.1 | Convert packed single data from zmm2/m512 to packed BF16 data in ymm1 with writemask k1. |
| Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| A | N/A | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
| B | Full | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
This instruction loads packed FP32 elements from a SIMD register or memory, converts the elements to BF16, and writes the result to the destination SIMD register.
The upper bits of the destination register beyond the down-converted BF16 elements are zeroed.
This instruction uses “Round to nearest (even)” rounding mode. Output denormals are always flushed to zero and input denormals are always treated as zero. MXCSR is not consulted nor updated.
As the instruction operand encoding table shows, the EVEX.vvvv field is not used for encoding an operand. EVEX.vvvv is reserved and must be 0b1111 otherwise instructions will #UD.
Define convert_fp32_to_bfloat16(x):
IF x is zero or denormal:
dest[15] ← x[31] // sign preserving zero (denormal go to zero)
dest[14:0] ← 0
ELSE IF x is infinity:
dest[15:0] ← x[31:16]
ELSE IF x is NAN:
dest[15:0] ← x[31:16] // truncate and set MSB of the mantissa to force QNAN
dest[6] ← 1
ELSE // normal number
LSB ← x[16]
rounding_bias ← 0x00007FFF + LSB
temp[31:0] ← x[31:0] + rounding_bias // integer add
dest[15:0] ← temp[31:16]
RETURN destVL = (128, 256)
KL = VL/16
FOR i ← 0 to KL/2-1:
t ← src.fp32[i]
dest.word[i] ← convert_fp32_to_bfloat16(t)VL = (128, 256, 512)
KL = VL/16
origdest ← dest
FOR i ← 0 to KL/2-1:
IF k1[ i ] or *no writemask*:
IF src is memory and evex.b == 1:
t ← src.fp32[0]
ELSE:
t ← src.fp32[ i ]
dest.word[i] ← convert_fp32_to_bfloat16(t)
ELSE IF *zeroing*:
dest.word[ i ] ← 0
ELSE: // Merge masking, dest element unchanged
dest.word[ i ] ← origdest.word[ i ]VCVTNEPS2BF16 __m128bh _mm_cvtneps_avx_pbh (__m128 __A);
VCVTNEPS2BF16 __m128bh _mm256_cvtneps_avx_pbh (__m256 __A);
VCVTNEPS2BF16 __m128bh _mm_cvtneps_pbh (__m128 a);
VCVTNEPS2BF16 __m128bh _mm_cvtneps_pbh (__m128 __A);
VCVTNEPS2BF16 __m128bh _mm_mask_cvtneps_pbh (__m128bh src, __mmask8 k, __m128 a);
VCVTNEPS2BF16 __m128bh _mm_maskz_cvtneps_pbh (__mmask8 k, __m128 a);
VCVTNEPS2BF16 __m128bh _mm256_cvtneps_pbh (__m256 a);
VCVTNEPS2BF16 __m128bh _mm256_cvtneps_pbh (__m256 __A);
VCVTNEPS2BF16 __m128bh _mm256_mask_cvtneps_pbh (__m128bh src, __mmask8 k, __m256 a);
VCVTNEPS2BF16 __m128bh _mm256_maskz_cvtneps_pbh (__mmask8 k, __m256 a);
VCVTNEPS2BF16 __m256bh _mm512_cvtneps_pbh (__m512 a);
VCVTNEPS2BF16 __m256bh _mm512_mask_cvtneps_pbh (__m256bh src, __mmask16 k, __m512 a);
VCVTNEPS2BF16 __m256bh _mm512_maskz_cvtneps_pbh (__mmask16 k, __m512 a);None.
Source: Intel® 64 and IA-32 Architectures Software Developer's Manual, Combined Volumes (Order Number 325462-091US, March 2026)
Generated: 7-6-2026