Split DMA RegisterAccess trait into RX/TX#2249
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bugadani
approved these changes
Sep 30, 2024
bugadani
reviewed
Oct 24, 2024
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| self.rx_impl | ||
| .prepare_transfer_without_start(preparation.start, peri) | ||
| compiler_fence(core::sync::atomic::Ordering::SeqCst); |
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Why do we need this fence? All operations around here are volatile, so non-reorderable
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Putting aside the "it was there before I touched it"
The fence is to make sure the descriptor and buffer setup (which is non-volatile) happens before the DMA starts.
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Pull Request Details 📖
Description
First two steps of #2248 and builds on top of #2247.
The
RegisterAccesstrait has been split intoRxRegisterAccess,TxRegisterAccessandInterruptAccess.And the new trait now take
&self.Testing
It builds, it's just an internal refactor.