PENDING: arm64: dts: qcom: glymur: add TGU and ETR in staging dtso

arch/arm64/boot/dts/qcom/Makefile

@@ -392,3 +392,72 @@ x1p42100-lenovo-thinkbook-16-el2-dtbs	:= x1p42100-lenovo-thinkbook-16.dtb x1-el2
 dtb-$(CONFIG_ARCH_QCOM)	+= x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb
 x1p64100-microsoft-denali-el2-dtbs	:= x1p64100-microsoft-denali.dtb x1-el2.dtbo
 dtb-$(CONFIG_ARCH_QCOM)	+= x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb
+
+hamoa-evk-camx-dtbs  := hamoa-iot-evk.dtb hamoa-evk-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= hamoa-evk-camx.dtb
+
+lemans-evk-camx-dtbs	:= lemans-evk.dtb lemans-evk-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= lemans-evk-camx.dtb
+
+lemans-camx-el2-dtbs	:= lemans-evk-el2.dtb lemans-evk-camx.dtbo lemans-camx-el2.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= lemans-camx-el2.dtb
+
+dtb-$(CONFIG_ARCH_QCOM)	+= lemans-evk-staging.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= lemans-staging.dtbo
+
+monaco-evk-camx-dtbs   := monaco-evk.dtb monaco-evk-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camx.dtb
+
+monaco-camx-el2-dtbs	:= monaco-evk-el2.dtb monaco-evk-camx.dtbo monaco-camx-el2.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= monaco-camx-el2.dtb
+
+dtb-$(CONFIG_ARCH_QCOM)	+= monaco-evk-staging.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= monaco-staging.dtbo
+
+qcs615-ride-camx-dtbs	:= qcs615-ride.dtb qcs615-ride-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs615-ride-camx.dtb
+
+qcs6490-rb3gen2-vision-mezzanine-camx-dtbs := qcs6490-rb3gen2-vision-mezzanine.dtb \
+						      qcs6490-rb3gen2-vision-mezzanine-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine-camx.dtb
+
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2-staging.dtbo
+
+qcs8300-ride-camx-dtbs:= qcs8300-ride.dtb qcs8300-ride-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-camx.dtb
+
+qcs9100-ride-camx-dtbs:= qcs9100-ride.dtb sa8775p-ride-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride-camx.dtb
+
+qcs9100-ride-r3-camx-dtbs:= qcs9100-ride-r3.dtb sa8775p-ride-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride-r3-camx.dtb
+
+sa8775p-ride-camx-dtbs:= sa8775p-ride.dtb sa8775p-ride-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= sa8775p-ride-camx.dtb
+
+sa8775p-ride-r3-camx-dtbs:= sa8775p-ride-r3.dtb sa8775p-ride-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= sa8775p-ride-r3-camx.dtb
+
+talos-evk-camx-dtbs	:= talos-evk.dtb talos-evk-camx.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM)	+= talos-evk-camx.dtb
+
+dtb-$(CONFIG_ARCH_QCOM) += talos-staging.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM) += kodiak-staging.dtbo
+
+dtb-$(CONFIG_ARCH_QCOM) += glymur-staging.dtbo

arch/arm64/boot/dts/qcom/glymur-staging.dtso

@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ * Glymur staging overlay - add staging-specific device tree modifications here.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&soc {
+	ctcu@10001000 {
+		compatible = "qcom,glymur-ctcu", "qcom,sa8775p-ctcu";
+		reg = <0x0 0x10001000 0x0 0x1000>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				ctcu_in0: endpoint {
+					remote-endpoint = <&etr0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				ctcu_in1: endpoint {
+					remote-endpoint = <&etr1_out>;
+				};
+			};
+		};
+	};
+
+	replicator@10046000 {
+		compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+		reg = <0x0 0x10046000 0x0 0x1000>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				qdss_rep_in: endpoint {
+					remote-endpoint = <&swao_rep_out0>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				qdss_rep_out0: endpoint {
+					remote-endpoint = <&etr_rep_in>;
+				};
+			};
+		};
+	};
+
+	tmc@10048000 {
+		compatible = "arm,coresight-tmc", "arm,primecell";
+		reg = <0x0 0x10048000 0x0 0x1000>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		iommus = <&apps_smmu 0x00e0 0x0000>;
+
+		arm,scatter-gather;
+
+		in-ports {
+			port {
+				etr0_in: endpoint {
+					remote-endpoint = <&etr_rep_out0>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				etr0_out: endpoint {
+					remote-endpoint = <&ctcu_in0>;
+				};
+			};
+		};
+	};
+
+	replicator@1004e000 {
+		compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+		reg = <0x0 0x1004e000 0x0 0x1000>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				etr_rep_in: endpoint {
+					remote-endpoint = <&qdss_rep_out0>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				etr_rep_out0: endpoint {
+					remote-endpoint = <&etr0_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				etr_rep_out1: endpoint {
+					remote-endpoint = <&etr1_in>;
+				};
+			};
+		};
+	};
+
+	tmc@1004f000 {
+		compatible = "arm,coresight-tmc", "arm,primecell";
+		reg = <0x0 0x1004f000 0x0 0x1000>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		iommus = <&apps_smmu 0x0100 0x0000>;
+
+		arm,scatter-gather;
+
+		in-ports {
+			port {
+				etr1_in: endpoint {
+					remote-endpoint = <&etr_rep_out1>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				etr1_out: endpoint {
+					remote-endpoint = <&ctcu_in1>;
+				};
+			};
+		};
+	};
+
+	tgu@11c02000 {
+		compatible = "qcom,tgu", "arm,primecell";
+		reg = <0x0 0x11c02000 0x0 0x1000>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	replicator@11c06000 {
+		out-ports {
+			port@0 {
+				reg = <0>;
+
+				swao_rep_out0: endpoint {
+					remote-endpoint = <&qdss_rep_in>;
+				};
+			};
+		};
+	};
+
+	tgu@11c0e000 {
+		compatible = "qcom,tgu", "arm,primecell";
+		reg = <0x0 0x11c0e000 0x0 0x1000>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	tgu@11c0f000 {
+		compatible = "qcom,tgu", "arm,primecell";
+		reg = <0x0 0x11c0f000 0x0 0x1000>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	tgu@11c10000 {
+		compatible = "qcom,tgu", "arm,primecell";
+		reg = <0x0 0x11c10000 0x0 0x1000>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+};

arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/camera/msm-camera.h>
+
+&cam_cci0 {
+	/*cam0-cmk_imx577*/
+	qcom,cam-sensor0 {
+		compatible = "qcom,cam-sensor";
+		csiphy-sd-index = <1>;
+		sensor-position-roll = <0>;
+		sensor-position-pitch = <0>;
+		sensor-position-yaw = <180>;
+		cam_vio-supply = <&vreg_l4m_1p8>;
+		regulator-names = "cam_vio";
+		power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+		rgltr-cntrl-support;
+		pwm-switch;
+		rgltr-min-voltage = <1800000>;
+		rgltr-max-voltage = <1800000>;
+		rgltr-load-current = <120000>;
+		gpio-no-mux = <0>;
+		pinctrl-names = "cam_default", "cam_suspend";
+		pinctrl-0 = <&cam_sensor_mclk1_active &cam_sensor_active_rst1>;
+		pinctrl-1 = <&cam_sensor_mclk1_suspend &cam_sensor_suspend_rst1>;
+		gpios = <&tlmm 97 0>,
+			<&tlmm 110 0>,
+			<&tlmm 19 0>;
+		gpio-reset = <1>;
+		gpio-custom1 = <2>;
+		gpio-req-tbl-num = <0 1 2>;
+		gpio-req-tbl-flags = <1 0 0>;
+		gpio-req-tbl-label = "CAM_MCLK1",
+				     "CAMIF_RESET1",
+				     "CAM_CUSTOM1";
+		cci-master = <1>;
+		clocks = <&camcc CAM_CC_MCLK1_CLK>;
+		clock-names = "cam_clk";
+		clock-cntl-level = "nominal";
+		clock-rates = <24000000>;
+		cell-index = <0>;
+		status = "okay";
+	};
+};
+
+&soc {
+	qcom,cam-res-mgr {
+		compatible = "qcom,cam-res-mgr";
+		status = "okay";
+	};
+};