hal/stm32n6: add configuration options for CPU/NPU clock

[jmaksymowicz]

Description

IMPORTANT: with this change PLL3 is reserved for clocking internal buses, peripherals and timers. If any external project reconfigures or otherwise depends on PLL3, please modify it to use PLL4 which is shall be reserved for auxiliary use.

The change to PLL allocation allows CPU and NPU clocks to be decoupled from the rest of the system, so that e.g. timers don't need to be reconfigured along with the CPU. The only exception is the SysTick - but it's not used in the kernel, so it's not a big problem.

To allow increasing the frequency, voltage scaling needs to be set to high using PWR_CORE_CONFIG definition - it needs to be put into board_config.h. The constant also sets up the use of the chip's built-in SMPS (step-down power converter) which is unused on Nucleo boards, but must be enabled for pilot boards.

Once voltage scaling has been set appropriately, the frequency can be chosen by setting RCC_DEFAULT_CPU_CLOCK constant. Currently the only valid choices are 600 MHz (maximum when VOS low) and 800 MHz (maximum when VOS high). These settings also configure the NPU and AXISRAM3/4/5/6 clocks:

• CPU == 600 MHz => NPU = 800 MHz, AXISRAM = 800 MHz
• CPU == 800 MHz => NPU = 1000 MHz, AXISRAM = 800 MHz.

If there is business need clocking can be expanded to:

• Allow setting of CPU and NPU clock separately
• Allow more granular frequency selection instead of just 2 choices
• Allow control of clocks at runtime (would require changes to kernel)

Motivation and Context

Increase CPU and NPU performance when requested.
YT: PP-512

Types of changes

• Bug fix (non-breaking change which fixes an issue)
• New feature (non-breaking change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)
• Chore (refactoring, style fixes, git/CI config, submodule management, no code logic changes)

How Has This Been Tested?

• Already covered by automatic testing.
• New test added: (add PR link here).
• Tested by hand on: armv8m55-stm32n6

Checklist:

• My change requires a change to the documentation.
• I have updated the documentation accordingly.
• I have added tests to cover my changes.
• All new and existing linter checks and tests passed.
• My changes generate no new compilation warnings for any of the targets.

Special treatment

• This PR needs additional PRs to work (list the PRs, preferably in merge-order).
• I will merge this PR by myself when appropriate.

[gemini-code-assist]

Code Review

This pull request introduces support for configuring the CPU clock frequency and power supply on the STM32N6 platform, adding the _stm32_rccSetCPUClock and _stm32_pwrGetCPUVolt functions along with pre-baked PLL configurations. The review feedback highlights a critical issue where PWR registers are accessed before the PWR peripheral clock is enabled, which would lead to a Bus Fault or Hard Fault. Additionally, a compile-time preprocessor check is suggested to prevent invalid clock and voltage configurations.

Important

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[github-actions]

Unit Test Results

10 860 tests  +275   10 190 ✅ +276   53m 6s ⏱️ -11s
   670 suites + 21      670 💤 ±  0 
     1 files   ±  0        0 ❌  -   1 

Results for commit 203fb1d. ± Comparison against base commit a139fa2.

This pull request removes 3 and adds 278 tests. Note that renamed tests count towards both.

phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit
phoenix-rtos-tests/libcache/unit ‑ armv7m7-imxrt106x-evk:phoenix-rtos-tests/libcache/unit
phoenix-rtos-tests/libcache/unit ‑ armv7m7-imxrt117x-evk:phoenix-rtos-tests/libcache/unit

phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_callback_err.cache_cleanCallbackErr
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_callback_err.cache_flushCallbackErr
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_callback_err.cache_read_readCallbackErr
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_callback_err.cache_write_readCallbackErr
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_callback_err.cache_write_writeCallbackErr
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_clean.cache_clean_addrOutOfScope
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_clean.cache_clean_addrPartiallyInScope
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_clean.cache_clean_badAddrRange
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_clean.cache_clean_lines
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_deinit.cache_deinit_initalizedCache
…

♻️ This comment has been updated with latest results.