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Add post code monitor to new eSPI register. #2482

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Merged
nathanaelhuffman merged 1 commit into from
Apr 21, 2026
+118 −10
Merged

Add post code monitor to new eSPI register. #2482

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4 changes: 2 additions & 2 deletions drv/spartan7-loader/cosmo-seq/README.md
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
FPGA images and collateral are generated from:
[this sha](https://github.com/oxidecomputer/quartz/commit/02767a4124da4cb9b74905699611077ebcda620a)
[release](https://api.github.com/repos/oxidecomputer/quartz/releases/299218883)
[this sha](https://github.com/oxidecomputer/quartz/commit/55d533c1f6303cfeb35be3058ad54f9dec186c67)
[release](https://api.github.com/repos/oxidecomputer/quartz/releases/311444273)
Binary file modified drv/spartan7-loader/cosmo-seq/cosmo_seq.bz2
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113 changes: 105 additions & 8 deletions drv/spartan7-loader/cosmo-seq/espi_regs.json
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Expand Up @@ -261,10 +261,107 @@
},
{
"type": "reg",
"inst_name": "ipcc_to_host_usedwds",
"inst_name": "post_code_monitor",
"addr_offset": 40,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
{
"type": "field",
"inst_name": "bl_success_c_main",
"lsb": 0,
"msb": 0,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "0xee1000a0 - BL_SUCCESS_C_MAIN - Successfully entered Main. Sticky: set when post code is seen, cleared by hardware on new boot."
},
{
"type": "field",
"inst_name": "tp_proc_mem_after_mem_data_init",
"lsb": 1,
"msb": 1,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "0xea00e046 - TpProcMemAfterMemDataInit - memory data initialised. Sticky: set when post code is seen, cleared by hardware on new boot."
},
{
"type": "field",
"inst_name": "tp_abl7_resume_initialization",
"lsb": 2,
"msb": 2,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "0xea00e101 - TpAbl7ResumeInitialization - eMCR starting (not seen if no eMCR). Sticky: set when post code is seen, cleared by hardware on new boot."
},
{
"type": "field",
"inst_name": "tp_abl_memory_ddr_training_start",
"lsb": 3,
"msb": 3,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "0xea00e340 - TpAblMemoryDdrTrainingStart - seen instead of TpAbl7ResumeInitialization when no eMCR. Sticky: set when post code is seen, cleared by hardware on new boot."
},
{
"type": "field",
"inst_name": "tp_proc_cpu_optimized_boot_start",
"lsb": 4,
"msb": 4,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "0xea00e055 - TpProcCpuOptimizedBootStart. Sticky: set when post code is seen, cleared by hardware on new boot."
},
{
"type": "field",
"inst_name": "tp_abl4_apob",
"lsb": 5,
"msb": 5,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "0xea00e0c9 - TpAbl4Apob. Sticky: set when post code is seen, cleared by hardware on new boot."
},
{
"type": "field",
"inst_name": "bl_success_bios_load_complete",
"lsb": 6,
"msb": 6,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "0xee1000bb - BL_SUCCESS_BIOS_LOAD_COMPLETE. Sticky: set when post code is seen, cleared by hardware on new boot."
},
{
"type": "field",
"inst_name": "phbl_hello",
"lsb": 7,
"msb": 7,
"reset": 0,
"sw_access": "rw",
"se_onread": null,
"se_onwrite": null,
"desc": "0x1de90001 - PHBLhello. Sticky: set when post code is seen, cleared by hardware on new boot."
}
]
},
{
"type": "reg",
"inst_name": "ipcc_to_host_usedwds",
"addr_offset": 44,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
{
"type": "field",
Expand All @@ -282,7 +379,7 @@
{
"type": "reg",
"inst_name": "ipcc_host_to_sp_usedwds",
"addr_offset": 44,
"addr_offset": 48,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand All @@ -302,7 +399,7 @@
{
"type": "reg",
"inst_name": "ipcc_to_host_byte_cntr",
"addr_offset": 48,
"addr_offset": 52,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand All @@ -322,7 +419,7 @@
{
"type": "reg",
"inst_name": "ipcc_dummy_fill_en",
"addr_offset": 52,
"addr_offset": 56,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand All @@ -342,7 +439,7 @@
{
"type": "reg",
"inst_name": "ipcc_dummy_fill_count",
"addr_offset": 56,
"addr_offset": 60,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand All @@ -362,7 +459,7 @@
{
"type": "reg",
"inst_name": "LIVE_ESPI_STATUS",
"addr_offset": 60,
"addr_offset": 64,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand Down Expand Up @@ -503,7 +600,7 @@
{
"type": "reg",
"inst_name": "LAST_RESP_STATUS",
"addr_offset": 64,
"addr_offset": 68,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand Down Expand Up @@ -644,7 +741,7 @@
{
"type": "reg",
"inst_name": "oob_free_saw_full",
"addr_offset": 68,
"addr_offset": 72,
"regwidth": 32,
"min_accesswidth": 32,
"children": [
Expand Down
11 changes: 11 additions & 0 deletions drv/spartan7-loader/cosmo-seq/sequencer_regs.json
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Expand Up @@ -2471,6 +2471,17 @@
"se_onread": null,
"se_onwrite": null,
"desc": "sp5_mfg_mode_l live status, (From SP5 to FPGA)"
},
{
"type": "field",
"inst_name": "sp5_perst_l",
"lsb": 9,
"msb": 9,
"reset": null,
"sw_access": "r",
"se_onread": null,
"se_onwrite": null,
"desc": "sp5_perst_l live status, (From SP5 hotplug to FPGA)"
}
]
},
Expand Down
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