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    322 repositories

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •353•1.6k•53•21•Updated May 5, 2026May 5, 2026

    • gwaihir

      Public
      aka Lago-Mio
      C
      •
      Other
      •1•3•1•1•Updated May 5, 2026May 5, 2026

    • magia-sdk

      Public
      C
      •10•5•0•7•Updated May 5, 2026May 5, 2026

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •101•130•17•3•Updated May 5, 2026May 5, 2026

    • llvm-project

      Public
      C++
      •17k•15•7•1•Updated May 5, 2026May 5, 2026

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •365•9•0•3•Updated May 5, 2026May 5, 2026

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvector
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •182•515•94•10•Updated May 5, 2026May 5, 2026

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •196•741•24•6•Updated May 5, 2026May 5, 2026

    • pulp-c910

      Public
      PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem with several modificatio…
      SystemVerilog
      •
      Other
      •8•18•0•0•Updated May 5, 2026May 5, 2026

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •45•149•6•5•Updated May 5, 2026May 5, 2026

    • ManyRVData

      Public
      C
      •3•3•0•4•Updated May 5, 2026May 5, 2026

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      •
      Apache License 2.0
      •6•19•9•2•Updated May 5, 2026May 5, 2026

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •8•36•3•6•Updated May 5, 2026May 5, 2026

    • Insitu-Cache

      Public
      SystemVerilog
      •
      Other
      •2•5•0•0•Updated May 4, 2026May 4, 2026

    • auteur

      Public
      The avant-garde tensor unit?
      SystemVerilog
      •
      Other
      •0•1•0•0•Updated May 4, 2026May 4, 2026

    • redundancy_cells

      Public
      SystemVerilog IPs and Modules for architectural redundancy designs.
      SystemVerilog
      •
      Other
      •10•20•0•5•Updated May 4, 2026May 4, 2026

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulation
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •106•332•18•21•Updated May 4, 2026May 4, 2026

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •61•288•24•4•Updated May 4, 2026May 4, 2026

    • pulp-linux

      Public
      Build GNU/Linux for various PULP/Cheshire-based systems.
      C
      •1•3•4•0•Updated May 4, 2026May 4, 2026

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •35•113•5•3•Updated May 4, 2026May 4, 2026

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •941•22•1•8•Updated May 1, 2026May 1, 2026

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •59•366•25•9•Updated Apr 30, 2026Apr 30, 2026

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •20•16•5•7•Updated Apr 30, 2026Apr 30, 2026

    • Onnx4Deeploy

      Public
      A comprehensive framework for ONNX model generation, optimization, and deployment for Deeploy.
      Python
      •5•7•0•2•Updated Apr 29, 2026Apr 29, 2026

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •158•19•0•6•Updated Apr 29, 2026Apr 29, 2026

    • datamover

      Public
      SystemVerilog
      •
      Other
      •2•1•7•1•Updated Apr 29, 2026Apr 29, 2026

    • pulp-nn-mixed

      Public
      C
      •10•14•1•0•Updated Apr 29, 2026Apr 29, 2026

    • AraXL

      Public
      A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
      C
      •
      Other
      •5•7•1•1•Updated Apr 29, 2026Apr 29, 2026

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •23•35•5•7•Updated Apr 28, 2026Apr 28, 2026

    • dram_rtl_sim

      Public
      SystemVerilog
      •
      Other
      •10•19•1•1•Updated Apr 28, 2026Apr 28, 2026
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