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1 change: 1 addition & 0 deletions chipcompiler/data/workspace.py
Original file line number Diff line number Diff line change
Expand Up @@ -258,6 +258,7 @@ def init_workspace_config(workspace: Workspace) -> None:
json_write(workspace.config[f"{StepEnum.ROUTING.value}"], router)

rcx = json_read(workspace.config[f"{StepEnum.RCX.value}"])
rcx["pdk"] = "ics55" if workspace.pdk.name == "ics55" else ""
rcx["mapping_file"] = workspace.pdk.mapping_file
corners = deepcopy(workspace.pdk.corners)
rcx["corners"] = corners
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2 changes: 1 addition & 1 deletion chipcompiler/thirdparty/ecc-tools
Submodule ecc-tools updated 116 files
3 changes: 2 additions & 1 deletion chipcompiler/tools/ecc/configs/rcx.json
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
{
"pdk": "",
"thread_num": 64,
"output": "/RCX_ecc/output",
"mapping_file": "/corners/ICsprout_55LLULP_1P6M_5lc_V1p1_cell.map",
Expand Down Expand Up @@ -58,4 +59,4 @@
]
}
]
}
}
4 changes: 3 additions & 1 deletion chipcompiler/tools/ecc/module.py
Original file line number Diff line number Diff line change
Expand Up @@ -890,7 +890,9 @@ def is_rt_timing_enable(self, config : str):
########################################################################
# RCX api
########################################################################
def init_rcx(self, config: str):
def init_rcx(self, config: str, pdk: str = ""):
if pdk:
return self.ecc.init_rcx(config=config, pdk=pdk)
return self.ecc.init_rcx(config=config)

def run_rcx(self):
Expand Down
5 changes: 4 additions & 1 deletion chipcompiler/tools/ecc/runner.py
Original file line number Diff line number Diff line change
Expand Up @@ -791,7 +791,10 @@ def run_jsons_to_itf(ecc_module : ECCToolsModule) -> bool:
sub_flow.update_step(step_name=EccSubFlowEnum.run_rcx.value, state=StateEnum.Imcomplete)
result = False
else:
ecc_module.init_rcx(config=workspace.config.get(StepEnum.RCX.value, ""))
rcx_config_path = workspace.config.get(StepEnum.RCX.value, "")
rcx_config = json_read(rcx_config_path)
rcx_pdk = str(rcx_config.get("pdk", "") or "").strip()
ecc_module.init_rcx(config=rcx_config_path, pdk=rcx_pdk)
ecc_module.run_rcx()
ecc_module.report_rcx()
sub_flow.update_step(step_name=EccSubFlowEnum.run_rcx.value, state=StateEnum.Success)
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27 changes: 27 additions & 0 deletions test/test_ecc_tools_module.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,33 @@
from chipcompiler.tools.ecc.module import ECCToolsModule


class FakeEcc:
def __init__(self):
self.calls = []

def init_rcx(self, **kwargs):
self.calls.append(kwargs)
return True


def test_ecc_tools_module_imports_installed_native_extension():
module = ECCToolsModule()
assert module.get_ecc() is not None


def test_init_rcx_passes_pdk_when_configured():
module = ECCToolsModule.__new__(ECCToolsModule)
module.ecc = FakeEcc()

assert module.init_rcx(config="/tmp/rcx.json", pdk="ics55") is True

assert module.ecc.calls == [{"config": "/tmp/rcx.json", "pdk": "ics55"}]


def test_init_rcx_omits_empty_pdk_for_backward_compatibility():
module = ECCToolsModule.__new__(ECCToolsModule)
module.ecc = FakeEcc()

assert module.init_rcx(config="/tmp/rcx.json") is True

assert module.ecc.calls == [{"config": "/tmp/rcx.json"}]
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