chore: test reports and imm refs#268
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vezenovm wants to merge 10 commits intomv/brillig-execution-reportsfrom
Closed
chore: test reports and imm refs#268vezenovm wants to merge 10 commits intomv/brillig-execution-reportsfrom
vezenovm wants to merge 10 commits intomv/brillig-execution-reportsfrom
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⚠️ Performance Alert ⚠️
Possible performance regression was detected for benchmark 'Brillig Bytecode Size'.
Benchmark result of this commit is worse than the previous benchmark result exceeding threshold 1.01.
| Benchmark suite | Current: 4d24e60 | Previous: 00d4360 | Ratio |
|---|---|---|---|
assert_is_not_equal_BLS12_377Fq_Bench |
116 opcodes |
110 opcodes |
1.05 |
assert_is_not_equal_BLS12_377Fr_Bench |
103 opcodes |
97 opcodes |
1.06 |
assert_is_not_equal_BLS12_381Fq_Bench |
116 opcodes |
110 opcodes |
1.05 |
assert_is_not_equal_BLS12_381Fr_Bench |
103 opcodes |
97 opcodes |
1.06 |
assert_is_not_equal_BN254_Fq_Bench |
103 opcodes |
97 opcodes |
1.06 |
assert_is_not_equal_U2048_Bench |
198 opcodes |
192 opcodes |
1.03 |
assert_is_not_equal_U256_Bench |
105 opcodes |
99 opcodes |
1.06 |
assert_is_not_zero_BLS12_377Fq_Bench |
78 opcodes |
75 opcodes |
1.04 |
assert_is_not_zero_BLS12_377Fr_Bench |
71 opcodes |
68 opcodes |
1.04 |
assert_is_not_zero_BLS12_381Fq_Bench |
78 opcodes |
75 opcodes |
1.04 |
assert_is_not_zero_BLS12_381Fr_Bench |
71 opcodes |
68 opcodes |
1.04 |
assert_is_not_zero_BN254_Fq_Bench |
71 opcodes |
68 opcodes |
1.04 |
assert_is_not_zero_U2048_Bench |
178 opcodes |
175 opcodes |
1.02 |
assert_is_not_zero_U256_Bench |
73 opcodes |
70 opcodes |
1.04 |
assert_is_not_zero_integer_BLS12_377Fq_Bench |
69 opcodes |
66 opcodes |
1.05 |
assert_is_not_zero_integer_BLS12_377Fr_Bench |
63 opcodes |
60 opcodes |
1.05 |
assert_is_not_zero_integer_BLS12_381Fq_Bench |
69 opcodes |
66 opcodes |
1.05 |
assert_is_not_zero_integer_BLS12_381Fr_Bench |
63 opcodes |
60 opcodes |
1.05 |
assert_is_not_zero_integer_BN254_Fq_Bench |
63 opcodes |
60 opcodes |
1.05 |
assert_is_not_zero_integer_U2048_Bench |
153 opcodes |
150 opcodes |
1.02 |
assert_is_not_zero_integer_U256_Bench |
63 opcodes |
60 opcodes |
1.05 |
cmp_BLS12_377Fq_Bench |
291 opcodes |
285 opcodes |
1.02 |
cmp_BLS12_377Fr_Bench |
251 opcodes |
245 opcodes |
1.02 |
cmp_BLS12_381Fq_Bench |
291 opcodes |
285 opcodes |
1.02 |
cmp_BLS12_381Fr_Bench |
251 opcodes |
245 opcodes |
1.02 |
cmp_BN254_Fq_Bench |
251 opcodes |
245 opcodes |
1.02 |
cmp_U256_Bench |
251 opcodes |
245 opcodes |
1.02 |
is_zero_BLS12_377Fq_Bench |
80 opcodes |
77 opcodes |
1.04 |
is_zero_BLS12_377Fr_Bench |
71 opcodes |
68 opcodes |
1.04 |
is_zero_BLS12_381Fq_Bench |
80 opcodes |
77 opcodes |
1.04 |
is_zero_BLS12_381Fr_Bench |
71 opcodes |
68 opcodes |
1.04 |
is_zero_BN254_Fq_Bench |
71 opcodes |
68 opcodes |
1.04 |
is_zero_U2048_Bench |
190 opcodes |
187 opcodes |
1.02 |
is_zero_U256_Bench |
70 opcodes |
67 opcodes |
1.04 |
is_zero_integer_BLS12_377Fq_Bench |
64 opcodes |
61 opcodes |
1.05 |
is_zero_integer_BLS12_377Fr_Bench |
58 opcodes |
55 opcodes |
1.05 |
is_zero_integer_BLS12_381Fq_Bench |
64 opcodes |
61 opcodes |
1.05 |
is_zero_integer_BLS12_381Fr_Bench |
58 opcodes |
55 opcodes |
1.05 |
is_zero_integer_BN254_Fq_Bench |
58 opcodes |
55 opcodes |
1.05 |
is_zero_integer_U2048_Bench |
148 opcodes |
145 opcodes |
1.02 |
is_zero_integer_U256_Bench |
58 opcodes |
55 opcodes |
1.05 |
sqrt_U2048_Bench |
64 opcodes |
61 opcodes |
1.05 |
sqrt_U256_Bench |
49 opcodes |
46 opcodes |
1.07 |
to_be_bytes_BLS12_377Fq_Bench |
251 opcodes |
248 opcodes |
1.01 |
to_be_bytes_BLS12_377Fr_Bench |
201 opcodes |
198 opcodes |
1.02 |
to_be_bytes_BLS12_381Fq_Bench |
251 opcodes |
248 opcodes |
1.01 |
to_be_bytes_BLS12_381Fr_Bench |
201 opcodes |
198 opcodes |
1.02 |
to_be_bytes_BN254_Fq_Bench |
201 opcodes |
198 opcodes |
1.02 |
to_be_bytes_U2048_Bench |
201 opcodes |
198 opcodes |
1.02 |
to_be_bytes_U256_Bench |
209 opcodes |
206 opcodes |
1.01 |
to_le_bytes_BLS12_377Fq_Bench |
294 opcodes |
291 opcodes |
1.01 |
to_le_bytes_BLS12_377Fr_Bench |
244 opcodes |
241 opcodes |
1.01 |
to_le_bytes_BLS12_381Fq_Bench |
294 opcodes |
291 opcodes |
1.01 |
to_le_bytes_BLS12_381Fr_Bench |
244 opcodes |
241 opcodes |
1.01 |
to_le_bytes_BN254_Fq_Bench |
244 opcodes |
241 opcodes |
1.01 |
to_le_bytes_U2048_Bench |
241 opcodes |
238 opcodes |
1.01 |
to_le_bytes_U256_Bench |
252 opcodes |
249 opcodes |
1.01 |
validate_in_range_BLS12_377Fq_Bench |
80 opcodes |
77 opcodes |
1.04 |
validate_in_range_BLS12_377Fr_Bench |
70 opcodes |
67 opcodes |
1.04 |
validate_in_range_BLS12_381Fq_Bench |
80 opcodes |
77 opcodes |
1.04 |
validate_in_range_BLS12_381Fr_Bench |
70 opcodes |
67 opcodes |
1.04 |
validate_in_range_BN254_Fq_Bench |
70 opcodes |
67 opcodes |
1.04 |
validate_in_range_U2048_Bench |
220 opcodes |
217 opcodes |
1.01 |
validate_in_range_U256_Bench |
70 opcodes |
67 opcodes |
1.04 |
This comment was automatically generated by workflow using github-action-benchmark.
Contributor
Changes to number of Brillig opcodes executed
🧾 Summary (10% most significant diffs)
Full diff report 👇
|
This reverts commit d4ce9f5.
2 tasks
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Description
Problem*
Test whether the reports added in #267 are working and we have good results in #265
Summary*
Additional Context
PR Checklist*
cargo fmton default settings.