Fix spelling errors

docs/LangRef.rst

@@ -2927,7 +2927,7 @@ the same register to an output and an input. If this is not safe (e.g. if the
 assembly contains two instructions, where the first writes to one output, and
 the second reads an input and writes to a second output), then the "``&``"
 modifier must be used (e.g. "``=&r``") to specify that the output is an
-"early-clobber" output. Marking an ouput as "early-clobber" ensures that LLVM
+"early-clobber" output. Marking an output as "early-clobber" ensures that LLVM
 will not use the same register for any inputs (other than an input tied to this
 output).
 

docs/SPIR-V.rst

@@ -1420,11 +1420,11 @@ placed in the ``Uniform`` or ``UniformConstant`` storage class.
 
 - ``shared``
 
-  - This is a hint to the compiler. It will be ingored.
+  - This is a hint to the compiler. It will be ignored.
 
 - ``volatile``
 
-  - This is a hint to the compiler. It will be ingored.
+  - This is a hint to the compiler. It will be ignored.
 
 HLSL semantic and Vulkan ``Location``
 -------------------------------------

docs/YamlIO.rst

@@ -730,7 +730,7 @@ it is parsed. This allows dynamic types of nodes.  But the YAML I/O model uses
 static typing, so there are limits to how you can use tags with the YAML I/O
 model. Recently, we added support to YAML I/O for checking/setting the optional 
 tag on a map. Using this functionality it is even possbile to support different 
-mappings, as long as they are convertable.  
+mappings, as long as they are convertible.  
 
 To check a tag, inside your mapping() method you can use io.mapTag() to specify
 what the tag should be.  This will also add that tag when writing yaml.

include/dxc/Support/HLSLOptions.td

@@ -277,7 +277,7 @@ def dump_dependencies : Flag<["-", "/"], "M">, Flags<[CoreOption, DriverOption]>
 def write_dependencies : Flag<["-", "/"], "MD">, Flags<[CoreOption, DriverOption]>,
   HelpText<"Write a file with .d extension that will contain the list of the compilation target dependencies.">;
 def write_dependencies_to : JoinedOrSeparate<["-", "/"], "MF">, MetaVarName<"<file>">, Flags<[CoreOption, DriverOption]>,
-  HelpText<"Write the specfied file that will contain the list of the compilation target dependencies.">;
+  HelpText<"Write the specified file that will contain the list of the compilation target dependencies.">;
 def external_lib : Separate<["-", "/"], "external">, Group<hlslcore_Group>, Flags<[DriverOption, RewriteOption, HelpHidden]>,
   HelpText<"External DLL name to load for compiler support">;
 def external_fn : Separate<["-", "/"], "external-fn">, Group<hlslcore_Group>, Flags<[DriverOption, RewriteOption, HelpHidden]>,
@@ -424,7 +424,7 @@ def fspv_use_unknown_image_format
 def fvk_auto_shift_bindings: Flag<["-"], "fvk-auto-shift-bindings">, Group<spirv_Group>, Flags<[CoreOption, DriverOption]>,
   HelpText<"Apply fvk-*-shift to resources without an explicit register assignment.">;
 def Wno_vk_ignored_features : Joined<["-"], "Wno-vk-ignored-features">, Group<spirv_Group>, Flags<[CoreOption, DriverOption, HelpHidden]>,
-  HelpText<"Do not emit warnings for ingored features resulting from no Vulkan support">;
+  HelpText<"Do not emit warnings for ignored features resulting from no Vulkan support">;
 def Wno_vk_emulated_features : Joined<["-"], "Wno-vk-emulated-features">, Group<spirv_Group>, Flags<[CoreOption, DriverOption, HelpHidden]>,
   HelpText<"Do not emit warnings for emulated features resulting from no direct mapping">;
 def fspv_print_all: Flag<["-"], "fspv-print-all">, Group<spirv_Group>, Flags<[CoreOption, DriverOption]>,
@@ -564,9 +564,9 @@ def res_may_alias : Flag<["-", "/"], "res-may-alias">, Flags<[CoreOption]>, Grou
 def res_may_alias_ : Flag<["-", "/"], "res_may_alias">, Flags<[CoreOption, HelpHidden]>, Group<hlslcomp_Group>,
   HelpText<"Assume that UAVs/SRVs may alias">;
 def all_resources_bound : Flag<["-", "/"], "all-resources-bound">, Flags<[CoreOption]>, Group<hlslcomp_Group>,
-  HelpText<"Enables agressive flattening">;
+  HelpText<"Enables aggressive flattening">;
 def all_resources_bound_ : Flag<["-", "/"], "all_resources_bound">, Flags<[CoreOption, HelpHidden]>, Group<hlslcomp_Group>,
-  HelpText<"Enables agressive flattening">;
+  HelpText<"Enables aggressive flattening">;
 
 def setprivate : JoinedOrSeparate<["-", "/"], "setprivate">, Flags<[CoreOption, DriverOption]>, MetaVarName<"<file>">, Group<hlslutil_Group>,
   HelpText<"Private data to add to compiled shader blob">;

include/dxc/dxcapi.internal.h

@@ -276,7 +276,7 @@ CROSS_PLATFORM_UUIDOF(IDxcLangExtensions3,
                       "A1B19880-FB1F-4920-9BC5-50356483BAC1")
 struct IDxcLangExtensions3 : public IDxcLangExtensions2 {
 public:
-  /// Registers a semantic define which cannot be overriden using the flag
+  /// Registers a semantic define which cannot be overridden using the flag
   /// -override-opt-semdefs
   virtual HRESULT STDMETHODCALLTYPE
   RegisterNonOptSemanticDefine(LPCWSTR name) = 0;

include/llvm/CodeGen/MachineScheduler.h

@@ -148,7 +148,7 @@ class MachineSchedRegistry
 class ScheduleDAGMI;
 
 /// Define a generic scheduling policy for targets that don't provide their own
-/// MachineSchedStrategy. This can be overriden for each scheduling region
+/// MachineSchedStrategy. This can be overridden for each scheduling region
 /// before building the DAG.
 struct MachineSchedPolicy {
   // Allow the scheduler to disable register pressure tracking.

include/llvm/CodeGen/Passes.h

@@ -42,7 +42,7 @@ using legacy::PassManagerBase;
 ///
 /// The PassConfig API prefers dealing with IDs because they are safer and more
 /// efficient. IDs decouple configuration from instantiation. This way, when a
-/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
+/// pass is overridden, it isn't unnecessarily instantiated. It is also unsafe to
 /// refer to a Pass pointer after adding it to a pass manager, which deletes
 /// redundant pass instances.
 ///
@@ -194,7 +194,7 @@ class TargetPassConfig : public ImmutablePass {
   bool getEnableShrinkWrap() const;
 
   /// Return true if the default global register allocator is in use and
-  /// has not be overriden on the command line with '-regalloc=...'
+  /// has not be overridden on the command line with '-regalloc=...'
   bool usingDefaultRegAlloc() const;
 
   /// Add common target configurable passes that perform LLVM IR to IR
@@ -251,7 +251,7 @@ class TargetPassConfig : public ImmutablePass {
   /// codegen pass pipeline where targets may insert passes. Methods with
   /// out-of-line standard implementations are major CodeGen stages called by
   /// addMachinePasses. Some targets may override major stages when inserting
-  /// passes is insufficient, but maintaining overriden stages is more work.
+  /// passes is insufficient, but maintaining overridden stages is more work.
   ///
 
   /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
@@ -346,7 +346,7 @@ class TargetPassConfig : public ImmutablePass {
   ///                  machine verification pass afterwards.
   void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
 
-  /// addMachinePasses helper to create the target-selected or overriden
+  /// addMachinePasses helper to create the target-selected or overridden
   /// regalloc pass.
   FunctionPass *createRegAllocPass(bool Optimized);
 

include/llvm/ExecutionEngine/Orc/ExecutionUtils.h

@@ -151,7 +151,7 @@ class LocalCXXRuntimeOverrides {
     return nullptr;
   }
 
-  /// Run any destructors recorded by the overriden __cxa_atexit function
+  /// Run any destructors recorded by the overridden __cxa_atexit function
   /// (CXAAtExitOverride).
   void runDestructors();
 

include/llvm/IR/LegacyPassNameParser.h

@@ -52,7 +52,7 @@ class PassNameParser : public PassRegistrationListener,
     enumeratePasses();
   }
 
-  // ignorablePassImpl - Can be overriden in subclasses to refine the list of
+  // ignorablePassImpl - Can be overridden in subclasses to refine the list of
   // which passes we want to include.
   //
   virtual bool ignorablePassImpl(const PassInfo *P) const { return false; }

include/llvm/MC/MCSchedule.h

@@ -166,7 +166,7 @@ struct MCSchedModel {
 
   // LoadLatency is the expected latency of load instructions.
   //
-  // If MinLatency >= 0, this may be overriden for individual load opcodes by
+  // If MinLatency >= 0, this may be overridden for individual load opcodes by
   // InstrItinerary OperandCycles.
   unsigned LoadLatency;
   static const unsigned DefaultLoadLatency = 4;
@@ -175,7 +175,7 @@ struct MCSchedModel {
   // See TargetInstrInfo::isHighLatencyDef().
   // By default, this is set to an arbitrarily high number of cycles
   // likely to have some impact on scheduling heuristics.
-  // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
+  // If MinLatency >= 0, this may be overridden by InstrItinData OperandCycles.
   unsigned HighLatency;
   static const unsigned DefaultHighLatency = 10;
 

include/llvm/Pass.h

@@ -149,7 +149,7 @@ protected: raw_ostream *OSOverride; // HLSL Change
   ///
   virtual bool doInitialization(Module &)  { return false; }
 
-  /// doFinalization - Virtual method overriden by subclasses to do any
+  /// doFinalization - Virtual method overridden by subclasses to do any
   /// necessary clean up after all passes have run.
   ///
   virtual bool doFinalization(Module &) { return false; }
@@ -183,7 +183,7 @@ protected: raw_ostream *OSOverride; // HLSL Change
   void setResolver(AnalysisResolver *AR);
   AnalysisResolver *getResolver() const { return Resolver; }
 
-  /// getAnalysisUsage - This function should be overriden by passes that need
+  /// getAnalysisUsage - This function should be overridden by passes that need
   /// analysis information to do their job.  If a pass specifies that it uses a
   /// particular analysis result to this function, it can then use the
   /// getAnalysis<AnalysisType>() function, below.
@@ -278,7 +278,7 @@ class ModulePass : public Pass {
   Pass *createPrinterPass(raw_ostream &O,
                           const std::string &Banner) const override;
 
-  /// runOnModule - Virtual method overriden by subclasses to process the module
+  /// runOnModule - Virtual method overridden by subclasses to process the module
   /// being operated on.
   virtual bool runOnModule(Module &M) = 0;
 
@@ -300,7 +300,7 @@ class ModulePass : public Pass {
 ///
 class ImmutablePass : public ModulePass {
 public:
-  /// initializePass - This method may be overriden by immutable passes to allow
+  /// initializePass - This method may be overridden by immutable passes to allow
   /// them to perform various initialization actions they require.  This is
   /// primarily because an ImmutablePass can "require" another ImmutablePass,
   /// and if it does, the overloaded version of initializePass may get access to
@@ -338,7 +338,7 @@ class FunctionPass : public Pass {
   Pass *createPrinterPass(raw_ostream &O,
                           const std::string &Banner) const override;
 
-  /// runOnFunction - Virtual method overriden by subclasses to do the
+  /// runOnFunction - Virtual method overridden by subclasses to do the
   /// per-function processing of the pass.
   ///
   virtual bool runOnFunction(Function &F) = 0;
@@ -380,12 +380,12 @@ class BasicBlockPass : public Pass {
   ///
   virtual bool doInitialization(Function &);
 
-  /// runOnBasicBlock - Virtual method overriden by subclasses to do the
+  /// runOnBasicBlock - Virtual method overridden by subclasses to do the
   /// per-basicblock processing of the pass.
   ///
   virtual bool runOnBasicBlock(BasicBlock &BB) = 0;
 
-  /// doFinalization - Virtual method overriden by BasicBlockPass subclasses to
+  /// doFinalization - Virtual method overridden by BasicBlockPass subclasses to
   /// do any post processing needed after all passes have run.
   ///
   virtual bool doFinalization(Function &);

include/llvm/Support/CommandLine.h

@@ -178,7 +178,7 @@ class alias;
 class Option {
   friend class alias;
 
-  // handleOccurrences - Overriden by subclasses to handle the value passed into
+  // handleOccurrences - Overridden by subclasses to handle the value passed into
   // an argument.  Should return true if there was an error processing the
   // argument and the program should exit.
   //

include/llvm/Target/TargetLoweringObjectFile.h

@@ -105,7 +105,7 @@ class TargetLoweringObjectFile : public MCObjectFileInfo {
                                                    const Function &F) const;
 
   /// Targets should implement this method to assign a section to globals with
-  /// an explicit section specfied. The implementation of this method can
+  /// an explicit section specified. The implementation of this method can
   /// assume that GV->hasSection() is true.
   virtual MCSection *
   getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind,

include/llvm/Target/TargetOptions.h

@@ -172,7 +172,7 @@ namespace llvm {
     /// Emit target-specific trap instruction for 'unreachable' IR instructions.
     unsigned TrapUnreachable : 1;
 
-    /// FloatABIType - This setting is set by -float-abi=xxx option is specfied
+    /// FloatABIType - This setting is set by -float-abi=xxx option is specified
     /// on the command line. This setting may either be Default, Soft, or Hard.
     /// Default selects the target's default behavior. Soft selects the ABI for
     /// software floating point, but does not indicate that FP hardware may not

include/llvm/Target/TargetRegisterInfo.h

@@ -840,7 +840,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
     return false;
   }
 
-  /// eliminateFrameIndex - This method must be overriden to eliminate abstract
+  /// eliminateFrameIndex - This method must be overridden to eliminate abstract
   /// frame indices from instructions which may use them.  The instruction
   /// referenced by the iterator contains an MO_FrameIndex operand which must be
   /// eliminated by this method.  This method may modify or replace the

include/llvm/Target/TargetSchedule.td

@@ -67,7 +67,7 @@ def instregex;
 // coarse grained instruction cost model. Default values for the
 // properties are defined in MCSchedModel. A value of "-1" in the
 // target description's SchedMachineModel indicates that the property
-// is not overriden by the target.
+// is not overridden by the target.
 //
 // Target hooks allow subtargets to associate LoadLatency and
 // HighLatency with groups of opcodes.

lib/AsmParser/LLParser.cpp

@@ -2880,7 +2880,7 @@ bool LLParser::ParseValID(ValID &ID, PerFunctionState *PFS) {
         if (!ValTy->getScalarType()->isIntegerTy())
           return Error(ID.Loc, "getelementptr index must be an integer");
         if (ValTy->isVectorTy() != BaseType->isVectorTy())
-          return Error(ID.Loc, "getelementptr index type missmatch");
+          return Error(ID.Loc, "getelementptr index type mismatch");
         if (ValTy->isVectorTy()) {
           unsigned ValNumEl = ValTy->getVectorNumElements();
           unsigned PtrNumEl = BaseType->getVectorNumElements();

lib/CodeGen/Passes.cpp

@@ -480,7 +480,7 @@ void TargetPassConfig::addISelPrepare() {
 /// with nontrivial configuration or multiple passes are broken out below in
 /// add%Stage routines.
 ///
-/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
+/// Any TargetPassConfig::addXX routine may be overridden by the Target. The
 /// addPre/Post methods with empty header implementations allow injecting
 /// target-specific fixups just before or after major stages. Additionally,
 /// targets have the flexibility to change pass order within a stage by
@@ -707,7 +707,7 @@ FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
 }
 
 /// Return true if the default global register allocator is in use and
-/// has not be overriden on the command line with '-regalloc=...'
+/// has not be overridden on the command line with '-regalloc=...'
 bool TargetPassConfig::usingDefaultRegAlloc() const {
   return RegAlloc.getNumOccurrences() == 0;
 }

lib/CodeGen/RegAllocPBQP.cpp

@@ -301,7 +301,7 @@ class Interference : public PBQPRAConstraint {
     }
 
     while (!Inactive.empty()) {
-      // Tentatively grab the "next" interval - this choice may be overriden
+      // Tentatively grab the "next" interval - this choice may be overridden
       // below.
       IntervalInfo Cur = Inactive.top();
 

lib/CodeGen/TargetInstrInfo.cpp

@@ -815,7 +815,7 @@ bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
 }
 
 /// Both DefMI and UseMI must be valid.  By default, call directly to the
-/// itinerary. This may be overriden by the target.
+/// itinerary. This may be overridden by the target.
 int TargetInstrInfo::
 getOperandLatency(const InstrItineraryData *ItinData,
                   const MachineInstr *DefMI, unsigned DefIdx,

lib/IR/Constants.cpp

@@ -2056,11 +2056,11 @@ Constant *ConstantExpr::getGetElementPtr(Type *Ty, Constant *C,
   ArgVec.push_back(C);
   for (unsigned i = 0, e = Idxs.size(); i != e; ++i) {
     assert(Idxs[i]->getType()->isVectorTy() == ReqTy->isVectorTy() &&
-           "getelementptr index type missmatch");
+           "getelementptr index type mismatch");
     assert((!Idxs[i]->getType()->isVectorTy() ||
             ReqTy->getVectorNumElements() ==
             Idxs[i]->getType()->getVectorNumElements()) &&
-           "getelementptr index type missmatch");
+           "getelementptr index type mismatch");
     ArgVec.push_back(cast<Constant>(Idxs[i]));
   }
   const ConstantExprKeyType Key(Instruction::GetElementPtr, ArgVec, 0,

lib/IR/Verifier.cpp

@@ -502,7 +502,7 @@ void Verifier::visitGlobalVariable(const GlobalVariable &GV) {
       if (GV.hasInitializer()) {
         const Constant *Init = GV.getInitializer();
         const ConstantArray *InitArray = dyn_cast<ConstantArray>(Init);
-        Assert(InitArray, "wrong initalizer for intrinsic global variable",
+        Assert(InitArray, "wrong initializer for intrinsic global variable",
                Init);
         for (unsigned i = 0, e = InitArray->getNumOperands(); i != e; ++i) {
           Value *V = Init->getOperand(i)->stripPointerCastsNoFollowAliases();
@@ -1065,7 +1065,7 @@ void Verifier::visitDIGlobalVariable(const DIGlobalVariable &N) {
   if (auto *V = N.getRawVariable()) {
     Assert(isa<ConstantAsMetadata>(V) &&
                !isa<Function>(cast<ConstantAsMetadata>(V)->getValue()),
-           "invalid global varaible ref", &N, V);
+           "invalid global variable ref", &N, V);
   }
   if (auto *Member = N.getRawStaticDataMemberDeclaration()) {
     Assert(isa<DIDerivedType>(Member), "invalid static data member declaration",

lib/TableGen/TGParser.cpp

@@ -1296,7 +1296,7 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType,
       Init *Bit = Vals[i]->convertInitializerTo(BitRecTy::get());
       if (!Bit) {
         Error(BraceLoc, "Element #" + Twine(i) + " (" + Vals[i]->getAsString() +
-              ") is not convertable to a bit");
+              ") is not convertible to a bit");
         return nullptr;
       }
       NewBits.push_back(Bit);

lib/Transforms/Scalar/RewriteStatepointsForGC.cpp

@@ -2599,7 +2599,7 @@ static void computeLiveInValues(DominatorTree &DT, Function &F,
   } // while( !worklist.empty() )
 
 #ifndef NDEBUG
-  // Sanity check our ouput against SSA properties.  This helps catch any
+  // Sanity check our output against SSA properties.  This helps catch any
   // missing kills during the above iteration.
   for (BasicBlock &BB : F) {
     checkBasicSSA(DT, Data, BB);

lib/Transforms/Scalar/SROA.cpp

@@ -1932,7 +1932,7 @@ static bool canConvertValue(const DataLayout &DL, Type *OldTy, Type *NewTy) {
 static Value *convertValue(const DataLayout &DL, IRBuilderTy &IRB, Value *V,
                            Type *NewTy) {
   Type *OldTy = V->getType();
-  assert(canConvertValue(DL, OldTy, NewTy) && "Value not convertable to type");
+  assert(canConvertValue(DL, OldTy, NewTy) && "Value not convertible to type");
 
   if (OldTy == NewTy)
     return V;

test/Transforms/MergeFunc/fold-weak.ll

@@ -17,7 +17,7 @@ define weak i32 @add(i32 %x, i32 %y) {
 ; Don't replace a weak function use by another equivalent function. We don't
 ; know whether the symbol that will ulitmately be linked is equivalent - we
 ; don't know that the weak definition is the definitive definition or whether it
-; will be overriden by a stronger definition).
+; will be overridden by a stronger definition).
 
 ; CHECK-LABEL: define private i32 @0
 ; CHECK: add i32

test/Transforms/SROA/basictest.ll

@@ -1270,7 +1270,7 @@ define void @PR15674(i8* %data, i8* %src, i32 %size) {
 ; Arrange (via control flow) to have unmerged stores of a particular width to
 ; an alloca where we incrementally store from the end of the array toward the
 ; beginning of the array. Ensure that the final integer store, despite being
-; convertable to the integer type that we end up promoting this alloca toward,
+; convertible to the integer type that we end up promoting this alloca toward,
 ; doesn't get widened to a full alloca store.
 ; CHECK-LABEL: @PR15674(