print pci device name and intruduce EDPC config by winterddd · Pull Request #208 · mchehab/rasdaemon

winterddd · 2025-03-27T10:07:01Z

New aer log like follow:

        <...>-2682840 [125] ....     0.017661 aer_event 2025-03-27
17:34:44 +0800 0000:99:00.0 (Intel Corporation Device 0b60 -
vendor_id: 0x8086 device_id: 0xb60) Data Link Protocol Uncorrected
(Non-Fatal)

And introduce EDPC config in rasdaemon

New aer log like follow: <...>-2682840 [125] .... 0.017661 aer_event 2025-03-27 17:34:44 +0800 0000:99:00.0 (Intel Corporation Device 0b60 - vendor_id: 0x8086 device_id: 0xb60) Data Link Protocol Uncorrected (Non-Fatal) Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com>

axiqia · 2025-03-29T09:03:13Z

+#define PCI_EXP_DPC_CTL			0x06	/* DPC control */
+#define  PCI_EXP_DPC_CTL_EN_FATAL	0x0001	/* Enable trigger on ERR_FATAL message */
+#define  PCI_EXP_DPC_CTL_EN_NONFATAL	0x0002	/* Enable trigger on ERR_NONFATAL message */
+#define  PCI_EXP_DPC_CTL_INT_EN		0x0008	/* DPC Interrupt Enable */


Linux provides a header file for PCI-related constants and macros, including those for Downstream Port Containment (DPC). The relevant definitions for PCI_EXP_DPC_CTL and related constants can be found in the Linux kernel header file:

#include <linux/pci_regs.h>

axiqia · 2025-03-29T09:30:14Z

+		return;
+
+	control = pci_read_word(dev, cap->addr + PCI_EXP_DPC_CTL);
+	need_config = ((control & (PCI_EXP_DPC_CTL_INT_EN | PCI_EXP_DPC_CTL_EN_MASK)) == EDPC_CONTROL_CONFIG) ? 0 : 1;


PCI_EXP_DPC_CTL_INT_EN is set to enable msi or msix interrupt when DPC is triggered, we should not set it in firmware first.

The correct logic is check if PCI_EXP_DPC_CTL_EN_FATAL is set:
need_config = (control & PCI_EXP_DPC_CTL_EN_MASK) != PCI_EXP_DPC_CTL_EN_FATAL;

accepted and fixed

axiqia · 2025-03-29T09:34:59Z

+#define PCI_EXP_DPC_CTL_EN_MASK	(PCI_EXP_DPC_CTL_EN_FATAL | \
+	PCI_EXP_DPC_CTL_EN_NONFATAL)


I prefer hard code the mask with 0x3,aka bit 1:0

I use PCI_DPC_CTL_TRIGGER in pci/pci.h

axiqia · 2025-03-29T10:00:27Z

+
+	if (need_config) {
+		control &= ~(PCI_EXP_DPC_CTL_INT_EN | PCI_EXP_DPC_CTL_EN_MASK);
+		control |= EDPC_CONTROL_CONFIG;


just clear bit 1:0 and set PCI_EXP_DPC_CTL_EN_FATAL

axiqia · 2025-03-29T10:01:24Z

+	struct pci_filter *filter = NULL;
+	char *token, *err, pci_names[MAX_PATH + 1];
+
+	strscpy(pci_names, names, sizeof(names));


Use sizeof(pci_names) instead of sizeof(names) to ensure the destination buffer size is respected.

axiqia · 2025-03-31T01:38:41Z

+	for (dev = pacc->devices; dev; dev = dev->next) {
+		if (len) {
+			for (i = 0; i < len; i++)
+				if (pci_filter_match(&filter[i], dev))


CXL.io also supports PCIe Enhanced Downstream Port Containment (eDPC) to disable links upon
detecting uncorrectable errors to contain and enable recovery from such errors. Enabling eDPC is not
recommended in most CXL 2.0 systems because eDPC containment flow brings the link down, disrupting
CXL.cache and CXL.mem traffic which can lead to host timeouts.

https://computeexpresslink.org/wp-content/uploads/2023/12/CXL-RAS-Whitepaper-Post-WG-Revision_FINAL.pdf

Should we also add a filter to avoid enabling EDPC for CXL.mem and CXL.cache?

accept, test on qemu

System with EDPC enabled device can recovery from fatal aer error. Rasdaemon now helps users correctly configure EDPC functionality. Rasdaemon will enable EDPC for fatal error if PCIE_EDPC_ENABLE set to 1. All device with EDPC capability will be enabled by default if EDPC_DEVICE is specified, only the specified device will be enabled. For example: PCIE_EDPC_ENABLE=1 EDPC_DEVICE=0000:01:00.0 only enable device 0000:01:00.0. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com>

axiqia · 2025-04-27T08:10:33Z

+			pci_fill_info(dev, PCI_FILL_IDENT);
+			*vendor_id = dev->vendor_id;
+			*device_id = dev->device_id;
+			pci_lookup_name(pacc, pci_name, len,


The cost to iterate all devices for each event is painful, do you consider adding a cache for bdf to device info?

axiqia · 2025-04-27T09:49:10Z

+	pci_init(pacc);
+	pci_scan_bus(pacc);
+
+	pci_names = getenv(EDPC_DEVICE);


I think you mean pci_names to pci_bdf_names

axiqia · 2025-04-27T09:52:24Z

+{
+	struct pci_access *pacc;
+	struct pci_dev *dev, *dev_head, *tmp;
+	int ret = 0, len = 1, i;


I prefer to init len = 0

axiqia · 2025-04-27T09:56:27Z

+	token = strtok(pci_names, ",");
+	while (token) {
+		pci_filter_init(pacc, &filter[i]);
+		err = pci_filter_parse_slot(&filter[i++], token);


add a check to filter out pcie device and only collect down stream port

axiqia · 2025-04-27T09:58:29Z

+	}
+
+	pci_cleanup(pacc);
+	free(filter);


filter is double freed, the first is in config_pcie_edpc_device, line 135

mchehab · 2025-11-14T12:42:03Z

This one didn't apply. Please rebase on the top of upstream:

ras-pcie-edpc.c: In function ‘is_cxl_mem_or_cache’:
ras-pcie-edpc.c:44:50: error: ‘PCI_CXL_CAP’ undeclared (first use in this function); did you mean ‘PCI_DLF_CAP’?
44 | cxl_cap = pci_read_word(dev, cap->addr + PCI_CXL_CAP);
| ^~~~~~~~~~~
| PCI_DLF_CAP
ras-pcie-edpc.c:44:50: note: each undeclared identifier is reported only once for each function it appears in
ras-pcie-edpc.c:45:24: error: ‘PCI_CXL_CAP_CACHE’ undeclared (first use in this function); did you mean ‘PCI_CXL_FB_CAP_CACHE’?
45 | if (cxl_cap & (PCI_CXL_CAP_CACHE | PCI_CXL_CAP_MEM))
| ^~~~~~~~~~~~~~~~~
| PCI_CXL_FB_CAP_CACHE
ras-pcie-edpc.c:45:44: error: ‘PCI_CXL_CAP_MEM’ undeclared (first use in this function); did you mean ‘PCI_CXL_FB_CAP_MEM’?
45 | if (cxl_cap & (PCI_CXL_CAP_CACHE | PCI_CXL_CAP_MEM))
| ^~~~~~~~~~~~~~~
| PCI_CXL_FB_CAP_MEM
ras-pcie-edpc.c: In function ‘cxl_check_rp’:
ras-pcie-edpc.c:66:38: error: ‘struct pci_dev’ has no member named ‘aux’
66 | dpc_p->aux = (void *)true;
| ^~
ras-pcie-edpc.c: In function ‘config_pcie_edpc’:
ras-pcie-edpc.c:193:25: error: ‘struct pci_dev’ has no member named ‘aux’
193 | if (!dev->aux) {
| ^~

axiqia reviewed Mar 31, 2025

View reviewed changes

winterddd force-pushed the aer branch 2 times, most recently from c84ffde to 2e91426 Compare March 31, 2025 08:01

winterddd force-pushed the aer branch from 2e91426 to 9554ad8 Compare April 14, 2025 10:10

winterddd force-pushed the aer branch from 9554ad8 to b8cefed Compare April 14, 2025 10:33

axiqia reviewed Apr 27, 2025

View reviewed changes

mchehab added the waiting new version label Nov 14, 2025

		#define PCI_EXP_DPC_CTL_EN_MASK (PCI_EXP_DPC_CTL_EN_FATAL \| \
		PCI_EXP_DPC_CTL_EN_NONFATAL)

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winterddd commented Mar 27, 2025

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mchehab commented Nov 14, 2025

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