π Electronics & Communication Engineering Student | VLSI & Physical Design Enthusiast
π‘ Focused on backend VLSI, RTL to GDSII, physical design automation, and AI-assisted product engineering.
π Creator of YouDO β The Aspirant Execution Companion.
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π― YouDO β Aspirant Execution Companion
A focused execution and goal-planning companion for serious aspirants. Build flexible goal trees, schedule daily work, run pause-aware focus sessions, review honest progress, and optionally join a privacy-conscious public focus Board. -
π» 8-bit RISC-V Inspired CPU (RTL to GDSII)
Open-source RISC-V digital design flow using Yosys & OpenROAD. -
β‘ 4-bit ALU RTL to GDSII
Digital logic ALU implementation targetting SkyWater 130nm PDK.
- VLSI & Hardware: Verilog, Yosys, OpenROAD, OpenSTA, SkyWater PDK
- Product & App Delivery: AI-Assisted Engineering, Android APK Build Pipelines, PWA Deployment
π Always open to exciting hardware & software engineering collaborations!

