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[Clean-ups] Few cleanups in tb.sv #478

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Merged
martin-velay merged 2 commits into from
Apr 30, 2026
Merged

[Clean-ups] Few cleanups in tb.sv #478

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c23ed05
[Clean-ups] Removed the unused peripheral clock interface
KinzaQamar Apr 28, 2026
bef3380
[chip, I2C, dv] Make sram_axi_sim use the right clock and reset
KinzaQamar Apr 28, 2026
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1 change: 0 additions & 1 deletion hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,6 @@ task top_chip_dv_base_vseq::apply_reset(string kind = "HARD");
begin : isolation_fork
fork
cfg.sys_clk_vif.apply_reset();
cfg.peri_clk_vif.apply_reset();
join_none
wait fork;
end : isolation_fork
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4 changes: 0 additions & 4 deletions hw/top_chip/dv/env/top_chip_dv_env.sv
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Expand Up @@ -67,10 +67,6 @@ function void top_chip_dv_env::build_phase(uvm_phase phase);
`uvm_fatal(`gfn, "Cannot get sys_clk_vif")
end

if (!uvm_config_db#(virtual clk_rst_if)::get(this, "", "peri_clk_if", cfg.peri_clk_vif)) begin
`uvm_fatal(`gfn, "Cannot get peri_clk_vif")
end

// Instantiate UART agent
m_uart_agent = uart_agent::type_id::create("m_uart_agent", this);
uvm_config_db#(uart_agent_cfg)::set(this, "m_uart_agent*", "cfg", cfg.m_uart_agent_cfg);
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1 change: 0 additions & 1 deletion hw/top_chip/dv/env/top_chip_dv_env_cfg.sv
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Expand Up @@ -8,7 +8,6 @@ class top_chip_dv_env_cfg extends uvm_object;

// External interfaces
virtual clk_rst_if sys_clk_vif;
virtual clk_rst_if peri_clk_vif;

// GPIO Pads interface
virtual pins_if #(NUM_GPIOS) gpio_vif;
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17 changes: 10 additions & 7 deletions hw/top_chip/dv/tb/tb.sv
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Expand Up @@ -24,8 +24,6 @@ module tb;
// ------ Signals ------
wire clk;
wire rst_n;
wire peri_clk;
wire peri_rst_n;

// GPIO connections
wire [NUM_GPIOS-1:0] gpio_pads; // A wire connected to bidirectional pads in pins_if
Expand All @@ -37,7 +35,6 @@ module tb;

// ------ Interfaces ------
clk_rst_if sys_clk_if(.clk(clk), .rst_n(rst_n));
clk_rst_if peri_clk_if(.clk(peri_clk), .rst_n(peri_rst_n));
uart_if uart_if();
pins_if #(NUM_GPIOS) gpio_pins_if (.pins(gpio_pads));

Expand Down Expand Up @@ -105,16 +102,24 @@ module tb;
end

// Signals to connect the sink
logic sim_sram_clk;
logic sim_sram_rst;
top_pkg::axi_req_t sim_sram_cpu_req;
top_pkg::axi_resp_t sim_sram_cpu_resp;
top_pkg::axi_req_t sim_sram_xbar_req;
top_pkg::axi_resp_t sim_sram_xbar_resp;

// CVA6 and Xbar uses clk_main_infra from clock manager and their request and response ports are
// interfaced in sim_sram_axi_sink module. Thus, use the same clock and reset as them to stay in
// sync.
assign sim_sram_clk = dut.clkmgr_clocks.clk_main_infra;
assign sim_sram_rst = dut.rstmgr_resets.rst_main_n[rstmgr_pkg::Domain0Sel];
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@martin-velay martin-velay Apr 29, 2026

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Another very nit: could you jump a line between the assigns and the comment below.
And maybe write a comment above these assign to explain why we need to connect to these internal DUT signals


// Instantiate the AXI sink to intercept the AXI traffic within the simulation memory range
// to provide a dedicated channel for SW-to-DV communication.
sim_sram_axi_sink u_sim_sram (
.clk_i (clk ),
.rst_ni (rst_n ),
.clk_i (sim_sram_clk ),
.rst_ni (sim_sram_rst ),
.cpu_req_i (sim_sram_cpu_req ),
.cpu_resp_o (sim_sram_cpu_resp ),
.xbar_req_o (sim_sram_xbar_req ),
Expand Down Expand Up @@ -226,10 +231,8 @@ module tb;

// Start clock and reset generators
sys_clk_if.set_active();
peri_clk_if.set_active();

uvm_config_db#(virtual clk_rst_if)::set(null, "*", "sys_clk_if", sys_clk_if);
uvm_config_db#(virtual clk_rst_if)::set(null, "*", "peri_clk_if", peri_clk_if);
uvm_config_db#(virtual uart_if)::set(null, "*.env.m_uart_agent*", "vif", uart_if);
uvm_config_db#(virtual pins_if #(NUM_GPIOS))::set(null, "*.env", "gpio_vif", gpio_pins_if);

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