Skip to content

[FMV][AArch64] Remove feature sha1 from FMV.#108383

Merged
labrinea merged 7 commits into
llvm:mainfrom
labrinea:fmv-remove-sha1
Sep 27, 2024
Merged

[FMV][AArch64] Remove feature sha1 from FMV.#108383
labrinea merged 7 commits into
llvm:mainfrom
labrinea:fmv-remove-sha1

Conversation

@labrinea
Copy link
Copy Markdown
Contributor

@labrinea labrinea commented Sep 12, 2024

Sha1 has been unified with sha2 in the ACLE spec
(see ARM-software/acle#347)
so I am changing the compiler to adhere to it.

@labrinea
[FMV][AArch64] Remove feature sha1 from FMV.
50820f4 
Sha1 has been unified with sha2 in the ACLE spec
(see ARM-software/acle#347)
so I am changing the compiler to adhere to it.
@llvmbot llvmbot added clang Clang issues not falling into any other category compiler-rt backend:AArch64 compiler-rt:builtins labels Sep 12, 2024
@llvmbot
Copy link
Copy Markdown
Member

llvmbot commented Sep 12, 2024 •
edited
Loading

@llvm/pr-subscribers-clang

@llvm/pr-subscribers-backend-aarch64

Author: Alexandros Lamprineas (labrinea)

Changes

Sha1 has been unified with sha2 in the ACLE spec
(see ARM-software/acle#347)
so I am changing the compiler to adhere to it.

Patch is 60.07 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/108383.diff

14 Files Affected:

  • (modified) clang/test/CodeGen/aarch64-cpu-supports.c (+6-6)
  • (modified) clang/test/CodeGen/aarch64-fmv-dependencies.c (-3)
  • (modified) clang/test/CodeGen/aarch64-mixed-target-attributes.c (+6-6)
  • (modified) clang/test/CodeGen/attr-target-clones-aarch64.c (+52-52)
  • (modified) clang/test/CodeGen/attr-target-version.c (+66-66)
  • (modified) clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp (+12-12)
  • (modified) clang/test/CodeGenCXX/attr-target-version.cpp (+8-8)
  • (modified) clang/test/CodeGenCXX/fmv-namespace.cpp (+4-4)
  • (modified) clang/test/Sema/attr-target-clones-aarch64.c (+3-3)
  • (modified) clang/test/Sema/attr-target-version.c (+2-2)
  • (modified) compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc (-1)
  • (modified) compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc (-2)
  • (modified) llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc (-1)
  • (modified) llvm/lib/Target/AArch64/AArch64FMV.td (-1)
diff --git a/clang/test/CodeGen/aarch64-cpu-supports.c b/clang/test/CodeGen/aarch64-cpu-supports.c
index c54b7475a3fd5f..e02c54917f4515 100644
--- a/clang/test/CodeGen/aarch64-cpu-supports.c
+++ b/clang/test/CodeGen/aarch64-cpu-supports.c
@@ -8,8 +8,8 @@
 // CHECK-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 35184372088832
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 35184372088832
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
 // CHECK:       if.then:
@@ -17,8 +17,8 @@
 // CHECK-NEXT:    br label [[RETURN:%.*]]
 // CHECK:       if.end:
 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 9070970929152
-// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 9070970929152
+// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 4535485464576
+// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4535485464576
 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 // CHECK-NEXT:    br i1 [[TMP7]], label [[IF_THEN1:%.*]], label [[IF_END2:%.*]]
 // CHECK:       if.then1:
@@ -26,8 +26,8 @@
 // CHECK-NEXT:    br label [[RETURN]]
 // CHECK:       if.end2:
 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP9:%.*]] = and i64 [[TMP8]], 166633186212708352
-// CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 166633186212708352
+// CHECK-NEXT:    [[TMP9:%.*]] = and i64 [[TMP8]], 83316593106354176
+// CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 83316593106354176
 // CHECK-NEXT:    [[TMP11:%.*]] = and i1 true, [[TMP10]]
 // CHECK-NEXT:    br i1 [[TMP11]], label [[IF_THEN3:%.*]], label [[IF_END4:%.*]]
 // CHECK:       if.then3:
diff --git a/clang/test/CodeGen/aarch64-fmv-dependencies.c b/clang/test/CodeGen/aarch64-fmv-dependencies.c
index e39c7adbe4a9b0..89b2b36dd987c7 100644
--- a/clang/test/CodeGen/aarch64-fmv-dependencies.c
+++ b/clang/test/CodeGen/aarch64-fmv-dependencies.c
@@ -117,9 +117,6 @@ __attribute__((target_version("rpres"))) int fmv(void) { return 0; }
 // CHECK: define dso_local i32 @fmv._Msb() #[[sb:[0-9]+]] {
 __attribute__((target_version("sb"))) int fmv(void) { return 0; }
 
-// CHECK: define dso_local i32 @fmv._Msha1() #[[ATTR0:[0-9]+]] {
-__attribute__((target_version("sha1"))) int fmv(void) { return 0; }
-
 // CHECK: define dso_local i32 @fmv._Msha2() #[[sha2:[0-9]+]] {
 __attribute__((target_version("sha2"))) int fmv(void) { return 0; }
 
diff --git a/clang/test/CodeGen/aarch64-mixed-target-attributes.c b/clang/test/CodeGen/aarch64-mixed-target-attributes.c
index d779abd395b5fb..c86877fe455ffd 100644
--- a/clang/test/CodeGen/aarch64-mixed-target-attributes.c
+++ b/clang/test/CodeGen/aarch64-mixed-target-attributes.c
@@ -66,8 +66,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
 // CHECK-NEXT:  resolver_entry:
 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 524288
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 524288
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK:       resolver_return:
@@ -140,8 +140,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
 // CHECK-NEXT:  resolver_entry:
 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 524288
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 524288
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK:       resolver_return:
@@ -207,8 +207,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
 // CHECK-NEXT:  resolver_entry:
 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 524288
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 524288
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK:       resolver_return:
diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c b/clang/test/CodeGen/attr-target-clones-aarch64.c
index 274e05de594b8e..5ea0a1aecc0e2b 100644
--- a/clang/test/CodeGen/attr-target-clones-aarch64.c
+++ b/clang/test/CodeGen/attr-target-clones-aarch64.c
@@ -62,16 +62,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-NEXT:  resolver_entry:
 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 16512
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16512
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 8320
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 8320
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK:       resolver_return:
 // CHECK-NEXT:    ret ptr @ftc._MaesMlse
 // CHECK:       resolver_else:
 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736
-// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 68719476736
+// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 34359738368
+// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 34359738368
 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 // CHECK:       resolver_return1:
@@ -96,16 +96,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-NEXT:  resolver_entry:
 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 17592186048512
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186048512
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 8796093024256
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 8796093024256
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK:       resolver_return:
 // CHECK-NEXT:    ret ptr @ftc_def._Mmemtag2Msha2
 // CHECK:       resolver_else:
 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 4096
-// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4096
+// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 2048
+// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2048
 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 // CHECK:       resolver_return1:
@@ -124,8 +124,8 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-NEXT:  resolver_entry:
 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 4096
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 2048
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2048
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK:       resolver_return:
@@ -184,16 +184,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-NEXT:  resolver_entry:
 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 562949953421312
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 562949953421312
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK:       resolver_return:
 // CHECK-NEXT:    ret ptr @ftc_dup3._Mbti
 // CHECK:       resolver_else:
 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416
-// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416
+// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 8796093022208
+// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 8796093022208
 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 // CHECK:       resolver_return1:
@@ -290,16 +290,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-NEXT:  resolver_entry:
 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 549757911040
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 549757911040
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 274878955520
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 274878955520
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK:       resolver_return:
 // CHECK-NEXT:    ret ptr @ftc_inline2._MfcmaMsve2-bitperm
 // CHECK:       resolver_else:
 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 65536
-// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 65536
+// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 32768
+// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 32768
 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 // CHECK:       resolver_return1:
@@ -336,16 +336,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-NEXT:  resolver_entry:
 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 18014535948435456
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014535948435456
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 9007267974217728
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 9007267974217728
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK:       resolver_return:
 // CHECK-NEXT:    ret ptr @ftc_inline1._Msve2-aesMwfxt
 // CHECK:       resolver_else:
 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 140737492549632
-// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 140737492549632
+// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 70368746274816
+// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 70368746274816
 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 // CHECK:       resolver_return1:
@@ -384,16 +384,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-NEXT:  resolver_entry:
 // CHECK-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 70369817919488
-// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817919488
+// CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 35184908959744
+// CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 35184908959744
 // CHECK-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK:       resolver_return:
 // CHECK-NEXT:    ret ptr @ftc_inline3._MsbMsve
 // CHECK:       resolver_else:
 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
-// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624
+// CHECK-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 562949953421312
+// CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 562949953421312
 // CHECK-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 // CHECK-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 // CHECK:       resolver_return1:
@@ -484,16 +484,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-MTE-BTI-NEXT:  resolver_entry:
 // CHECK-MTE-BTI-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-MTE-BTI-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-MTE-BTI-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 16512
-// CHECK-MTE-BTI-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16512
+// CHECK-MTE-BTI-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 8320
+// CHECK-MTE-BTI-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 8320
 // CHECK-MTE-BTI-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-MTE-BTI-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK-MTE-BTI:       resolver_return:
 // CHECK-MTE-BTI-NEXT:    ret ptr @ftc._MaesMlse
 // CHECK-MTE-BTI:       resolver_else:
 // CHECK-MTE-BTI-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-MTE-BTI-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736
-// CHECK-MTE-BTI-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 68719476736
+// CHECK-MTE-BTI-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 34359738368
+// CHECK-MTE-BTI-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 34359738368
 // CHECK-MTE-BTI-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 // CHECK-MTE-BTI-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 // CHECK-MTE-BTI:       resolver_return1:
@@ -518,16 +518,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-MTE-BTI-NEXT:  resolver_entry:
 // CHECK-MTE-BTI-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-MTE-BTI-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-MTE-BTI-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 17592186048512
-// CHECK-MTE-BTI-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186048512
+// CHECK-MTE-BTI-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 8796093024256
+// CHECK-MTE-BTI-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 8796093024256
 // CHECK-MTE-BTI-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-MTE-BTI-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK-MTE-BTI:       resolver_return:
 // CHECK-MTE-BTI-NEXT:    ret ptr @ftc_def._Mmemtag2Msha2
 // CHECK-MTE-BTI:       resolver_else:
 // CHECK-MTE-BTI-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-MTE-BTI-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 4096
-// CHECK-MTE-BTI-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4096
+// CHECK-MTE-BTI-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 2048
+// CHECK-MTE-BTI-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2048
 // CHECK-MTE-BTI-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 // CHECK-MTE-BTI-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 // CHECK-MTE-BTI:       resolver_return1:
@@ -546,8 +546,8 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-MTE-BTI-NEXT:  resolver_entry:
 // CHECK-MTE-BTI-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-MTE-BTI-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-MTE-BTI-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 4096
-// CHECK-MTE-BTI-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
+// CHECK-MTE-BTI-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 2048
+// CHECK-MTE-BTI-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2048
 // CHECK-MTE-BTI-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-MTE-BTI-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK-MTE-BTI:       resolver_return:
@@ -606,16 +606,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-MTE-BTI-NEXT:  resolver_entry:
 // CHECK-MTE-BTI-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-MTE-BTI-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-MTE-BTI-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 1125899906842624
-// CHECK-MTE-BTI-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1125899906842624
+// CHECK-MTE-BTI-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 562949953421312
+// CHECK-MTE-BTI-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 562949953421312
 // CHECK-MTE-BTI-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-MTE-BTI-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK-MTE-BTI:       resolver_return:
 // CHECK-MTE-BTI-NEXT:    ret ptr @ftc_dup3._Mbti
 // CHECK-MTE-BTI:       resolver_else:
 // CHECK-MTE-BTI-NEXT:    [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-MTE-BTI-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416
-// CHECK-MTE-BTI-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416
+// CHECK-MTE-BTI-NEXT:    [[TMP5:%.*]] = and i64 [[TMP4]], 8796093022208
+// CHECK-MTE-BTI-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 8796093022208
 // CHECK-MTE-BTI-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
 // CHECK-MTE-BTI-NEXT:    br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 // CHECK-MTE-BTI:       resolver_return1:
@@ -712,16 +712,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
 // CHECK-MTE-BTI-NEXT:  resolver_entry:
 // CHECK-MTE-BTI-NEXT:    call void @__init_cpu_features_resolver()
 // CHECK-MTE-BTI-NEXT:    [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
-// CHECK-MTE-BTI-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 549757911040
-// CHECK-MTE-BTI-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 549757911040
+// CHECK-MTE-BTI-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 274878955520
+// CHECK-MTE-BTI-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 274878955520
 // CHECK-MTE-BTI-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
 // CHECK-MTE-BTI-NEXT:    br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 // CHECK-MTE-BTI:       resolver_return:
 // CHECK-MTE-BTI-NEXT:    ret ptr @ftc_inline2._MfcmaMsve2-bitperm
 // CHECK-MTE-BTI:       resolver_else:
 // CHECK-MTE-BTI-NEXT:    [[TMP4...
[truncated]

@labrinea labrinea mentioned this pull request Sep 12, 2024
Merged
efriedma-quic
efriedma-quic reviewed Sep 12, 2024
View reviewed changes
Comment thread compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc
@labrinea labrinea mentioned this pull request Sep 13, 2024
Closed
@labrinea
Merge branch 'main' into fmv-remove-sha1
3fb81b4
@labrinea
Changes from last revision:
6c0485d 
Bring back FEAT_SHA1 as reserved bit to preserve ABI compatibility.
@labrinea
Copy link
Copy Markdown
Contributor Author

labrinea commented Sep 23, 2024

ping

@labrinea labrinea merged commit e2cc63d into llvm:main Sep 27, 2024
@labrinea labrinea deleted the fmv-remove-sha1 branch September 27, 2024 15:31
@llvm-ci
Copy link
Copy Markdown

llvm-ci commented Sep 27, 2024

LLVM Buildbot has detected a new failure on builder fuchsia-x86_64-linux running on fuchsia-debian-64-us-central1-a-1 while building clang,compiler-rt,llvm at step 4 "annotate".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/11/builds/5749

Here is the relevant piece of the build log for the reference 
Step 4 (annotate) failure: 'python ../llvm-zorg/zorg/buildbot/builders/annotated/fuchsia-linux.py ...' (failure)
...
[263/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/aarch64/sme-abi-vg.c.obj
[264/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/udivdi3.c.obj
[265/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/aarch64/sme-libc-routines.c.obj
[266/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/udivsi3.c.obj
[267/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/umoddi3.c.obj
[268/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/umodsi3.c.obj
[269/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/divtf3.c.obj
[270/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/truncdfhf2.c.obj
[271/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_ldset1_1.S.obj
[272/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/cpu_model/aarch64.c.obj
FAILED: CMakeFiles/clang_rt.builtins-aarch64.dir/cpu_model/aarch64.c.obj 
/var/lib/buildbot/fuchsia-x86_64-linux/build/llvm-build-vziw39xw/bin/clang --target=aarch64-unknown-fuchsia --sysroot=/usr/local/fuchsia/sdk/arch/arm64/sysroot -DHAS_ASM_LSE -DVISIBILITY_HIDDEN  --target=aarch64-unknown-fuchsia -I/usr/local/fuchsia/sdk/pkg/sync/include -I/usr/local/fuchsia/sdk/pkg/fdio/include -O2 -g -DNDEBUG -fno-lto -std=c11 -fPIC -fno-builtin -fvisibility=hidden -fomit-frame-pointer -DCOMPILER_RT_HAS_FLOAT16 -MD -MT CMakeFiles/clang_rt.builtins-aarch64.dir/cpu_model/aarch64.c.obj -MF CMakeFiles/clang_rt.builtins-aarch64.dir/cpu_model/aarch64.c.obj.d -o CMakeFiles/clang_rt.builtins-aarch64.dir/cpu_model/aarch64.c.obj -c /var/lib/buildbot/fuchsia-x86_64-linux/llvm-project/compiler-rt/lib/builtins/cpu_model/aarch64.c
In file included from /var/lib/buildbot/fuchsia-x86_64-linux/llvm-project/compiler-rt/lib/builtins/cpu_model/aarch64.c:72:
/var/lib/buildbot/fuchsia-x86_64-linux/llvm-project/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/fuchsia.inc:28:19: error: use of undeclared identifier 'FEAT_SHA1'
   28 |     setCPUFeature(FEAT_SHA1);
      |                   ^
1 error generated.
[273/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/truncdfsf2.c.obj
[274/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/truncsfhf2.c.obj
[275/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/udivmoddi4.c.obj
[276/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/aarch64/sme-libc-mem-routines.S.obj
[277/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas1_4.S.obj
[278/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas1_2.S.obj
[279/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas2_3.S.obj
[280/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas2_2.S.obj
[281/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/aarch64/sme-abi.S.obj
[282/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/gcc_personality_v0.c.obj
[283/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas1_3.S.obj
[284/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas1_5.S.obj
[285/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas2_4.S.obj
[286/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas1_1.S.obj
[287/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas2_1.S.obj
[288/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas2_5.S.obj
[289/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas4_5.S.obj
[290/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas8_1.S.obj
[291/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas4_1.S.obj
[292/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas4_4.S.obj
[293/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas4_3.S.obj
[294/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas4_2.S.obj
[295/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas8_3.S.obj
[296/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/udivmodti4.c.obj
[297/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas8_5.S.obj
[298/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas16_1.S.obj
[299/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas8_2.S.obj
[300/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_swp1_1.S.obj
[301/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas16_5.S.obj
[302/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas8_4.S.obj
[303/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas16_4.S.obj
[304/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_swp1_4.S.obj
Step 6 (build) failure: build (failure)
...
[263/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/aarch64/sme-abi-vg.c.obj
[264/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/udivdi3.c.obj
[265/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/aarch64/sme-libc-routines.c.obj
[266/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/udivsi3.c.obj
[267/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/umoddi3.c.obj
[268/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/umodsi3.c.obj
[269/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/divtf3.c.obj
[270/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/truncdfhf2.c.obj
[271/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_ldset1_1.S.obj
[272/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/cpu_model/aarch64.c.obj
FAILED: CMakeFiles/clang_rt.builtins-aarch64.dir/cpu_model/aarch64.c.obj 
/var/lib/buildbot/fuchsia-x86_64-linux/build/llvm-build-vziw39xw/bin/clang --target=aarch64-unknown-fuchsia --sysroot=/usr/local/fuchsia/sdk/arch/arm64/sysroot -DHAS_ASM_LSE -DVISIBILITY_HIDDEN  --target=aarch64-unknown-fuchsia -I/usr/local/fuchsia/sdk/pkg/sync/include -I/usr/local/fuchsia/sdk/pkg/fdio/include -O2 -g -DNDEBUG -fno-lto -std=c11 -fPIC -fno-builtin -fvisibility=hidden -fomit-frame-pointer -DCOMPILER_RT_HAS_FLOAT16 -MD -MT CMakeFiles/clang_rt.builtins-aarch64.dir/cpu_model/aarch64.c.obj -MF CMakeFiles/clang_rt.builtins-aarch64.dir/cpu_model/aarch64.c.obj.d -o CMakeFiles/clang_rt.builtins-aarch64.dir/cpu_model/aarch64.c.obj -c /var/lib/buildbot/fuchsia-x86_64-linux/llvm-project/compiler-rt/lib/builtins/cpu_model/aarch64.c
In file included from /var/lib/buildbot/fuchsia-x86_64-linux/llvm-project/compiler-rt/lib/builtins/cpu_model/aarch64.c:72:
/var/lib/buildbot/fuchsia-x86_64-linux/llvm-project/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/fuchsia.inc:28:19: error: use of undeclared identifier 'FEAT_SHA1'
   28 |     setCPUFeature(FEAT_SHA1);
      |                   ^
1 error generated.
[273/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/truncdfsf2.c.obj
[274/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/truncsfhf2.c.obj
[275/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/udivmoddi4.c.obj
[276/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/aarch64/sme-libc-mem-routines.S.obj
[277/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas1_4.S.obj
[278/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas1_2.S.obj
[279/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas2_3.S.obj
[280/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas2_2.S.obj
[281/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/aarch64/sme-abi.S.obj
[282/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/gcc_personality_v0.c.obj
[283/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas1_3.S.obj
[284/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas1_5.S.obj
[285/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas2_4.S.obj
[286/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas1_1.S.obj
[287/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas2_1.S.obj
[288/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas2_5.S.obj
[289/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas4_5.S.obj
[290/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas8_1.S.obj
[291/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas4_1.S.obj
[292/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas4_4.S.obj
[293/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas4_3.S.obj
[294/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas4_2.S.obj
[295/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas8_3.S.obj
[296/407] Building C object CMakeFiles/clang_rt.builtins-aarch64.dir/udivmodti4.c.obj
[297/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas8_5.S.obj
[298/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas16_1.S.obj
[299/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas8_2.S.obj
[300/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_swp1_1.S.obj
[301/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas16_5.S.obj
[302/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas8_4.S.obj
[303/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_cas16_4.S.obj
[304/407] Building ASM object CMakeFiles/clang_rt.builtins-aarch64.dir/outline_atomic_helpers.dir/outline_atomic_swp1_4.S.obj

@labrinea
Copy link
Copy Markdown
Contributor Author

labrinea commented Sep 27, 2024

Fix here -> #110291

Sterling-Augustine pushed a commit to Sterling-Augustine/llvm-project that referenced this pull request Sep 27, 2024
@labrinea @Sterling-Augustine
[FMV][AArch64] Remove feature sha1 from FMV. (llvm#108383)
619eb8b 
Sha1 has been unified with sha2 in the ACLE spec
(see ARM-software/acle#347)
so I am changing the compiler to adhere to it.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@tommat01 tommat01 tommat01 approved these changes

@jroelofs jroelofs Awaiting requested review from jroelofs

@alicecarlotti alicecarlotti Awaiting requested review from alicecarlotti

@efriedma-quic efriedma-quic Awaiting requested review from efriedma-quic

Assignees

No one assigned

Labels

backend:AArch64 clang Clang issues not falling into any other category compiler-rt:builtins compiler-rt

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

7 participants

@labrinea @llvmbot @llvm-ci @jroelofs @alicecarlotti @efriedma-quic @tommat01