linuxboot · gaspar-ilom · Mar 9, 2025 · Mar 9, 2025 · Mar 9, 2025 · Mar 9, 2025
diff --git a/.circleci/config.yml b/.circleci/config.yml
@@ -414,29 +414,29 @@ workflows:
             - t480-hotp-maximized
 
       - build:
-          name: UNTESTED_t440p-maximized
-          target: UNTESTED_t440p-maximized
+          name: t440p-maximized
+          target: t440p-maximized
           subcommand: ""
           requires:
             - t480-hotp-maximized
 
       - build:
-          name: UNTESTED_t440p-hotp-maximized
-          target: UNTESTED_t440p-hotp-maximized
+          name: t440p-hotp-maximized
+          target: t440p-hotp-maximized
           subcommand: ""
           requires:
             - t480-hotp-maximized
 
       - build:
-          name: UNTESTED_w541-maximized
-          target: UNTESTED_w541-maximized
+          name: w541-maximized
+          target: w541-maximized
           subcommand: ""
           requires:
             - t480-hotp-maximized
 
       - build:
-          name: UNTESTED_w541-hotp-maximized
-          target: UNTESTED_w541-hotp-maximized
+          name: w541-hotp-maximized
+          target: w541-hotp-maximized
           subcommand: ""
           requires:
             - t480-hotp-maximized

diff --git a/BOARD_TESTERS.md b/BOARD_TESTERS.md
@@ -30,7 +30,7 @@ xx30 (Ivy):
 
 xx4x(Haswell):
 ===
-- [ ] t440p: @fhvyhjriur @ThePlexus @srgrint @akunterkontrolle @rbreslow
+- [ ] t440p: @MattClifton76 @fhvyhjriur @ThePlexus @srgrint @akunterkontrolle @rbreslow
 - [ ] w541 (similar to t440p): @ResendeGHF @gaspar-ilom (Always tested late: Needs more responsive board testers or risk to become unmaintained.)
 
 xx8x(Kaby Lake Refresh):

diff --git a/blobs/haswell/.gitignore b/blobs/haswell/.gitignore
diff --git a/blobs/haswell/obtain-mrc b/blobs/haswell/obtain-mrc
diff --git a/blobs/t440p/README.md b/blobs/t440p/README.md
@@ -7,14 +7,17 @@
 
 Coreboot on the T440p requires the following binary blobs:
 
-- `mrc.bin` - Consists of Intel’s Memory Reference Code (MRC) and [is used to initialize the DRAM](https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html).
 - `me.bin` - Consists of Intel’s Management Engine (ME), which we modify using [me_cleaner](https://github.com/corna/me_cleaner) to remove all but the modules which are necessary for the CPU to function.
 - `gbe.bin` - Consists of hardware/software configuration data for the Gigabit Ethernet (GbE) controller. Intel publishes the data structure [here](https://web.archive.org/web/20230122164346/https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/i-o-controller-hub-8-9-nvm-map-guide.pdf), and an [ImHex](https://github.com/WerWolv/ImHex) hex editor pattern is available [here](https://github.com/rbreslow/ImHex-Patterns/blob/rb/intel-ich8/patterns/intel/ich8_lan_nvm.hexpat).
 - `ifd.bin` - Consists of the Intel Flash Descriptor (IFD). Intel publishes the data structure [here](https://web.archive.org/web/20221208011432/https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/io-controller-hub-8-datasheet.pdf), and an ImHex hex editor pattern is available [here](https://github.com/rbreslow/ImHex-Patterns/blob/rb/intel-ich8/patterns/intel/ich8_flash_descriptor.hexpat).
 
 Heads supplies an IFD and GbE blob, which we extracted from a donor board. We changed the MAC address of the GbE blob to `00:de:ad:c0:ff:ee` using [nvmutil](https://libreboot.org/docs/install/nvmutil.html), to support anonymity and build reproducibility.
 
-When building any T440p board variant with `make`, the build system will download a copy of the MRC and Intel ME. We extract `mrc.bin` from a Chromebook firmware image and `me.bin` from a Lenovo firmware update.
+When building any T440p board variant with `make`, the build system will download a copy of the Intel ME. We extract the `me.bin` from a Lenovo firmware update.
+
+### Native Ram Initialization
+
+Note that due to native ram initialization for haswell boards in coreboot it is no longer necessary to use a third party blob (`mrc.bin`) for that.
 
 ## Using Your Own Blobs
 

diff --git a/blobs/w541/README.md b/blobs/w541/README.md
@@ -7,14 +7,17 @@
 
 Coreboot on the W541 requires the following binary blobs:
 
-- `mrc.bin` - Consists of Intel’s Memory Reference Code (MRC) and [is used to initialize the DRAM](https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html).
 - `me.bin` - Consists of Intel’s Management Engine (ME), which we modify using [me_cleaner](https://github.com/corna/me_cleaner) to remove all but the modules which are necessary for the CPU to function.
 - `gbe.bin` - Consists of hardware/software configuration data for the Gigabit Ethernet (GbE) controller. Intel publishes the data structure [here](https://web.archive.org/web/20230122164346/https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/i-o-controller-hub-8-9-nvm-map-guide.pdf), and an [ImHex](https://github.com/WerWolv/ImHex) hex editor pattern is available [here](https://github.com/rbreslow/ImHex-Patterns/blob/rb/intel-ich8/patterns/intel/ich8_lan_nvm.hexpat).
 - `ifd.bin` - Consists of the Intel Flash Descriptor (IFD). Intel publishes the data structure [here](https://web.archive.org/web/20221208011432/https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/io-controller-hub-8-datasheet.pdf), and an ImHex hex editor pattern is available [here](https://github.com/rbreslow/ImHex-Patterns/blob/rb/intel-ich8/patterns/intel/ich8_flash_descriptor.hexpat).
 
 Heads supplies an IFD and GbE blob, which we extracted from a donor board. We changed the MAC address of the GbE blob to `00:de:ad:c0:ff:ee` using [nvmutil](https://libreboot.org/docs/install/nvmutil.html), to support anonymity and build reproducibility.
 
-When building any W541 board variant with `make`, the build system will download a copy of the MRC and Intel ME. We extract `mrc.bin` from a Chromebook firmware image and `me.bin` from a Lenovo firmware update.
+When building any W541 board variant with `make`, the build system will download a copy of the Intel ME. We extract the `me.bin` from a Lenovo firmware update.
+
+### Native Ram Initialization
+
+Note that due to native ram initialization for haswell boards in coreboot it is no longer necessary to use a third party blob (`mrc.bin`)
 
 ## Using Your Own Blobs
 

diff --git a/...ized/UNTESTED_t440p-hotp-maximized.config → ...otp-maximized/t440p-hotp-maximized.config b/...ized/UNTESTED_t440p-hotp-maximized.config → ...otp-maximized/t440p-hotp-maximized.config
@@ -1,5 +1,5 @@
 # Inherit the rest from the base T440p config.
-include $(pwd)/boards/UNTESTED_t440p-maximized/UNTESTED_t440p-maximized.config
+include $(pwd)/boards/t440p-maximized/t440p-maximized.config
 
 CONFIG_HOTPKEY=y
 export CONFIG_AUTO_BOOT_TIMEOUT=5

diff --git a/...maximized/UNTESTED_t440p-maximized.config → ...ds/t440p-maximized/t440p-maximized.config b/...maximized/UNTESTED_t440p-maximized.config → ...ds/t440p-maximized/t440p-maximized.config
@@ -49,11 +49,7 @@ export CONFIG_FLASH_OPTIONS="flashprog --progress --programmer internal"
 
 # Make the Coreboot build depend on the following 3rd party blobs:
 $(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \
-    $(pwd)/blobs/haswell/mrc.bin $(pwd)/blobs/t440p/me.bin
-
-$(pwd)/blobs/haswell/mrc.bin:
-	COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \
-		$(pwd)/blobs/haswell/obtain-mrc $(pwd)/blobs/haswell
+    $(pwd)/blobs/t440p/me.bin
 
 $(pwd)/blobs/t440p/me.bin:
 	COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \

diff --git a/...mized/UNTESTED_w541-hotp-maximized.config → ...hotp-maximized/w541-hotp-maximized.config b/...mized/UNTESTED_w541-hotp-maximized.config → ...hotp-maximized/w541-hotp-maximized.config
@@ -1,5 +1,5 @@
 # Inherit the rest from the base W541 config.
-include $(pwd)/boards/UNTESTED_w541-maximized/UNTESTED_w541-maximized.config
+include $(pwd)/boards/w541-maximized/w541-maximized.config
 
 CONFIG_HOTPKEY=y
 export CONFIG_AUTO_BOOT_TIMEOUT=5

diff --git a/...-maximized/UNTESTED_w541-maximized.config → boards/w541-maximized/w541-maximized.config b/...-maximized/UNTESTED_w541-maximized.config → boards/w541-maximized/w541-maximized.config
@@ -49,11 +49,7 @@ export CONFIG_FLASH_OPTIONS="flashprog --progress --programmer internal"
 
 # Make the Coreboot build depend on the following 3rd party blobs:
 $(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \
-    $(pwd)/blobs/haswell/mrc.bin $(pwd)/blobs/w541/me.bin
-
-$(pwd)/blobs/haswell/mrc.bin:
-	COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \
-		$(pwd)/blobs/haswell/obtain-mrc $(pwd)/blobs/haswell
+    $(pwd)/blobs/w541/me.bin
 
 $(pwd)/blobs/w541/me.bin:
 	COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \

diff --git a/config/coreboot-t440p.config b/config/coreboot-t440p.config
@@ -153,9 +153,9 @@ CONFIG_MAX_SOCKET=1
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_TPM_PIRQ=0x0
 CONFIG_DCACHE_RAM_BASE=0xff7c0000
-CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_DCACHE_RAM_SIZE=0x40000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
+CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
 CONFIG_HAVE_INTEL_FIRMWARE=y
 CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
@@ -220,7 +220,6 @@ CONFIG_PS2K_EISAID="LEN0071"
 CONFIG_PS2M_EISAID="LEN0036"
 CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_LENOVO_TBFW_BIN=""
 CONFIG_D3COLD_SUPPORT=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
@@ -285,9 +284,7 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HAVE_MRC=y
-CONFIG_MRC_FILE="@BLOB_DIR@/haswell/mrc.bin"
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@@ -338,9 +335,7 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 # Northbridge
 #
 CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
-# CONFIG_USE_NATIVE_RAMINIT is not set
-# CONFIG_USE_BROADWELL_MRC is not set
-CONFIG_HASWELL_HIDE_PEG_FROM_MRC=y
+CONFIG_USE_NATIVE_RAMINIT=y
 
 #
 # Southbridge
@@ -584,7 +579,6 @@ CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y
 # CONFIG_BOOTMEDIA_LOCK_CHIP is not set
 CONFIG_BOOTMEDIA_LOCK_WHOLE_RO=y
 # CONFIG_BOOTMEDIA_LOCK_WHOLE_NO_ACCESS is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
 # end of Security
 
 CONFIG_ACPI_HAVE_PCAT_8259=y
@@ -609,22 +603,23 @@ CONFIG_SQUELCH_EARLY_SMP=y
 # CONFIG_CONSOLE_NE2K is not set
 CONFIG_CONSOLE_CBMEM=y
 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
+CONFIG_CONSOLE_SPI_FLASH=y
+CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE=0x20000
 # CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_EM100PRO_SPI_CONSOLE is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=6
 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
 CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-CONFIG_HWBASE_DEBUG_CB=y
+CONFIG_HWBASE_DEBUG_NULL=y
 # end of Console
 
 CONFIG_HAVE_ACPI_RESUME=y
@@ -696,9 +691,10 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
 # General Debug Settings
 #
 # CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set

diff --git a/config/coreboot-w541.config b/config/coreboot-w541.config
@@ -153,9 +153,9 @@ CONFIG_MAX_SOCKET=1
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_TPM_PIRQ=0x0
 CONFIG_DCACHE_RAM_BASE=0xff7c0000
-CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_DCACHE_RAM_SIZE=0x40000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
+CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
 CONFIG_HAVE_INTEL_FIRMWARE=y
 CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
@@ -220,7 +220,6 @@ CONFIG_PS2K_EISAID="LEN0071"
 CONFIG_PS2M_EISAID="LEN004A"
 CONFIG_THINKPADEC_HKEY_EISAID="LEN0068"
 CONFIG_GFX_GMA_PANEL_1_PORT="DP3"
-CONFIG_LENOVO_TBFW_BIN=""
 CONFIG_D3COLD_SUPPORT=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
 # CONFIG_DRIVERS_UART_8250IO is not set
@@ -285,9 +284,7 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HAVE_MRC=y
-CONFIG_MRC_FILE="@BLOB_DIR@/haswell/mrc.bin"
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@@ -338,9 +335,7 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 # Northbridge
 #
 CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
-# CONFIG_USE_NATIVE_RAMINIT is not set
-# CONFIG_USE_BROADWELL_MRC is not set
-CONFIG_HASWELL_HIDE_PEG_FROM_MRC=y
+CONFIG_USE_NATIVE_RAMINIT=y
 
 #
 # Southbridge
@@ -583,7 +578,6 @@ CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y
 # CONFIG_BOOTMEDIA_LOCK_CHIP is not set
 CONFIG_BOOTMEDIA_LOCK_WHOLE_RO=y
 # CONFIG_BOOTMEDIA_LOCK_WHOLE_NO_ACCESS is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
 # end of Security
 
 CONFIG_ACPI_HAVE_PCAT_8259=y
@@ -608,22 +602,23 @@ CONFIG_SQUELCH_EARLY_SMP=y
 # CONFIG_CONSOLE_NE2K is not set
 CONFIG_CONSOLE_CBMEM=y
 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
+CONFIG_CONSOLE_SPI_FLASH=y
+CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE=0x20000
 # CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_EM100PRO_SPI_CONSOLE is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=6
 CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
 CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-CONFIG_HWBASE_DEBUG_CB=y
+CONFIG_HWBASE_DEBUG_NULL=y
 # end of Console
 
 CONFIG_HAVE_ACPI_RESUME=y
@@ -695,9 +690,10 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
 # General Debug Settings
 #
 # CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set