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litespi: fix cs handling for bulk transfers #852

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litespi: fix cs handling for bulk transfers #852

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16 changes: 8 additions & 8 deletions litex/soc/cores/spi.py
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ def __init__(self, pads, data_width, sys_clk_freq, spi_clk_freq, with_csr=True,
self.irq = Signal()
self.mosi = Signal(data_width)
self.miso = Signal(data_width)
self.cs = Signal(len(pads.cs_n), reset=1)
self.cs = Signal(len(pads.cs_n))
self.loopback = Signal()
self.clk_divider = Signal(16, reset=math.ceil(sys_clk_freq/spi_clk_freq))

Expand All @@ -45,7 +45,7 @@ def __init__(self, pads, data_width, sys_clk_freq, spi_clk_freq, with_csr=True,
# # #

clk_enable = Signal()
cs_enable = Signal()
mosi_enable = Signal()
count = Signal(max=data_width)
mosi_latch = Signal()
miso_latch = Signal()
Expand Down Expand Up @@ -79,13 +79,13 @@ def __init__(self, pads, data_width, sys_clk_freq, spi_clk_freq, with_csr=True,
fsm.act("START",
NextValue(count, 0),
If(clk_fall,
cs_enable.eq(1),
mosi_enable.eq(1),
NextState("RUN")
)
)
fsm.act("RUN",
clk_enable.eq(1),
cs_enable.eq(1),
mosi_enable.eq(1),
If(clk_fall,
NextValue(count, count + 1),
If(count == (self.length - 1),
Expand All @@ -94,7 +94,7 @@ def __init__(self, pads, data_width, sys_clk_freq, spi_clk_freq, with_csr=True,
)
)
fsm.act("STOP",
cs_enable.eq(1),
mosi_enable.eq(1),
If(clk_rise,
miso_latch.eq(1),
self.irq.eq(1),
Expand All @@ -105,7 +105,7 @@ def __init__(self, pads, data_width, sys_clk_freq, spi_clk_freq, with_csr=True,
# Chip Select generation -------------------------------------------------------------------
if hasattr(pads, "cs_n"):
for i in range(len(pads.cs_n)):
self.sync += pads.cs_n[i].eq(~self.cs[i] | ~cs_enable)
self.sync += pads.cs_n[i].eq(~self.cs[i])

# Master Out Slave In (MOSI) generation (generated on spi_clk falling edge) ----------------
mosi_data = Signal(data_width)
Expand All @@ -116,7 +116,7 @@ def __init__(self, pads, data_width, sys_clk_freq, spi_clk_freq, with_csr=True,
mosi_data.eq(self.mosi),
mosi_sel.eq((self.length-1) if mode == "aligned" else (data_width-1)),
).Elif(clk_fall,
If(cs_enable, pads.mosi.eq(mosi_array[mosi_sel])),
If(mosi_enable, pads.mosi.eq(mosi_array[mosi_sel])),
mosi_sel.eq(mosi_sel - 1)
),
]
Expand Down Expand Up @@ -154,7 +154,7 @@ def add_csr(self, with_cs=True, with_loopback=True):
]
if with_cs:
self._cs = CSRStorage(fields=[
CSRField("sel", len(self.cs), reset=1, description="Write ``1`` to corresponding bit to enable Xfer for chip.")
CSRField("sel", len(self.cs), reset=0, description="Write ``1`` to corresponding bit to enable Xfer for chip.")
], description="SPI Chip Select.")
self.comb += self.cs.eq(self._cs.storage)
if with_loopback:
Expand Down
2 changes: 2 additions & 0 deletions test/test_spi.py
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Original file line number Diff line number Diff line change
Expand Up @@ -69,12 +69,14 @@ def master_generator(dut):
yield
yield dut.master.mosi.eq(0xdeadbeef)
yield dut.master.length.eq(32)
yield dut.master.cs.eq(1)
yield dut.master.start.eq(1)
yield
yield dut.master.start.eq(0)
yield
while (yield dut.master.done) == 0:
yield
yield dut.master.cs.eq(0)
yield
self.assertEqual(hex((yield dut.master.miso)), hex(0x12345678))

Expand Down