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_stm32_debug was ORIGIN(PPB)+0x42000 = 0xE0042000, the F4 DBGMCU address. On STM32H7 the core accesses DBGMCU at 0x5C001000 (0xE00E1000 is the debugger-only APB-D alias). The misplaced base made the timer2_stop_in_debug write in Timer::Initialize land on a dead address, so TIM2 never froze during debug halts, corrupting while-halted TIM2 SR/CNT observations. Work done by AI (opencode, deepseek-v4-flash-free, parameters and context window as configured): root-caused via linker .map + live DBGMCU dump, implemented the one-line _stm32_debug = 0x5C001000 change, verified on hardware (symbol binding, DBG_TIM2=1, ISR clear confirmed). Review/decision: human.
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Summary
_stm32_debug(and thereforestm32::h7xx::debug) was bound toORIGIN(PPB) + 0x42000=0xE0042000, the F4 DBGMCU address. On STM32H7 the core accesses DBGMCU at0x5C001000(0xE00E1000is the debugger-only APB-D alias).Impact
Timer::Initialize()(modules/stm32/source/Timer2.cpp) setstimer2_stop_in_debug = 1, but the write landed on a dead address.APB1LFZ1.DBG_TIM2stayed 0, so TIM2 free-ran during debug halts — corrupting all while-halted TIM2 SR/CNT/overflow observations and making the timer look grossly inaccurate under debug.Fix
_stm32_debug = 0x5C001000;with an explanatory comment.Verification (on hardware via pylink-square-mcp)
stm32::h7xx::debugbinds to0x5C001000APB1LFZ1.DBG_TIM2 = 1after bootHost unit tests 19/19 (LLVM + AppleClang); M4/M7 cross tests build. Fixes #50.