[bacescuandrei]

Three aarch64 semantics differences from the architecture, found by comparing the python jitter with Unicorn 2.1.4 on single instructions:

• ANDS, BICS and TST set N and Z but left C and V unchanged. The Arm ARM defines NZCV = result<N-1>:IsZero(result):'00' for these, so C and V are now cleared.
• EXTR Xd, Xn, Xm, #lsb extracts from Xn:Xm, with Xn as the high part. The semantics built ExprCompose(arg2, arg3), which puts Xn in the low part; for example EXTR X0, X1, X2, 1 with X1 = 1, X2 = 0 gave 0 instead of 0x8000000000000000.
• UDIV and SDIV with a zero divisor raised EXCEPT_DIV_BY_ZERO. On AArch64 division by zero does not trap and the result is 0 (if IsZero(operand2) then result = 0).

Added unit tests test/arch/aarch64/unit/mn_ands.py, mn_extr.py and mn_div.py and listed them in test/test_all.py. With the master semantics all three fail with both the python and gcc jitters; with this change they pass with both, and mn_ubfm.py still passes. (When switching between the two versions the gcc jitter's block cache in /tmp/miasm_cache has to be cleared, otherwise blocks compiled with the old semantics are reused.)

With this change, 252,072 single-instruction cases of the aarch64 differential comparison no longer show differences for these instructions. The miasm encodings of the ANDS, EXTR and SDIV cases were checked with llvm-mc.