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175 changes: 175 additions & 0 deletions tests/assembly_params.json
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{
"_comment": "Synthetic MSP430 instruction costs. Every value is derived from the cost model below and chosen to produce the outcomes the tests assert on, so treat them as fixed inputs rather than as an estimate of any real device.",
"_cost_model": "cost = 1.5 * units. A register-only instruction is 1 unit. An immediate source adds 1, an indirect/autoincrement source adds 1, and an indexed/symbolic/absolute source adds 2. A memory destination adds the same, plus 1 more when the instruction reads it back (everything except mov/cmp/bit). Jumps are 2 units. Outside that model: push/pop/br are 3, 2 and 3 units; nop/dint/clrc/ret/reti are 1 unit; adjcallstackdown/adjcallstackup are 0 because they expand to no code when every argument is register-passed, which holds for the snippets in tests/. Library calls are listed individually, scaled so __mspabi_divi and the other division helpers exceed any E_safe a test config can produce and a block containing one cannot fit a single charge.",
"_adding_a_key": "Derive the value from the model above. A key absent here costs defaultEnergy_ (1.0) and only warns, so tests/test_rockclimb.py asserts the pass reports zero missing keys.",
"ignored_call_targets": [
"_timing_delay_cycles",
"bench_commit_done",
"bench_halt",
"debug_exit",
"debug_exit_commit",
"debug_init",
"timing_gpio_init",
"timing_gpio_start",
"timing_gpio_stop"
],
"parameters": {
"adc_indexed": 6.0,
"add_absolute_register": 4.5,
"add_autoincrement_register": 3.0,
"add_immediate_indexed": 7.5,
"add_immediate_register": 3.0,
"add_indexed_register": 4.5,
"add_indirect_register": 3.0,
"add_register_absolute": 6.0,
"add_register_indexed": 6.0,
"add_register_register": 1.5,
"addc_immediate_register": 3.0,
"addc_register_register": 1.5,
"adjcallstackdown": 0.0,
"adjcallstackup": 0.0,
"and_absolute_register": 4.5,
"and_immediate_absolute": 7.5,
"and_immediate_register": 3.0,
"and_indexed_register": 4.5,
"and_register_register": 1.5,
"and_symbolic_absolute": 9.0,
"and_symbolic_register": 4.5,
"bic_immediate_absolute": 7.5,
"bic_immediate_register": 3.0,
"bic_register_register": 1.5,
"bic_symbolic_register": 4.5,
"bis_immediate_absolute": 7.5,
"bis_immediate_register": 3.0,
"bis_indexed_indexed": 9.0,
"bis_indexed_register": 4.5,
"bis_register_indexed": 6.0,
"bis_register_register": 1.5,
"bis_symbolic_absolute": 9.0,
"bis_symbolic_register": 4.5,
"bit_immediate_absolute": 6.0,
"bit_immediate_indexed": 6.0,
"bit_immediate_register": 3.0,
"bit_symbolic_absolute": 7.5,
"bit_symbolic_indexed": 7.5,
"bit_symbolic_register": 4.5,
"br_immediate": 4.5,
"br_indexed": 4.5,
"call___mspabi_addd": 3000.0,
"call___mspabi_addf": 600.0,
"call___mspabi_cvtdf": 1200.0,
"call___mspabi_cvtfd": 300.0,
"call___mspabi_divd": 6000.0,
"call___mspabi_divf": 750.0,
"call___mspabi_divi": 750.0,
"call___mspabi_divli": 3000.0,
"call___mspabi_divu": 750.0,
"call___mspabi_fixfli": 150.0,
"call___mspabi_fltuld": 300.0,
"call___mspabi_fltulf": 300.0,
"call___mspabi_mpyd": 12000.0,
"call___mspabi_mpyf": 1500.0,
"call___mspabi_mpyi": 30.0,
"call___mspabi_mpyl": 45.0,
"call___mspabi_mpyll": 45.0,
"call___mspabi_remu": 750.0,
"call___mspabi_remul": 3000.0,
"call___mspabi_subd": 3000.0,
"call_cos": 600000.0,
"call_immediate": 18.0,
"call_memcpy": 18.0,
"call_memcpy_bytes": 12.0,
"call_memset": 18.0,
"call_memset_bytes": 12.0,
"call_sin": 600000.0,
"clr_register": 1.5,
"clrc": 1.5,
"cmp_absolute_indexed": 7.5,
"cmp_immediate_absolute": 6.0,
"cmp_immediate_indexed": 6.0,
"cmp_immediate_register": 3.0,
"cmp_indexed_indexed": 7.5,
"cmp_indexed_register": 4.5,
"cmp_register_indexed": 4.5,
"cmp_register_register": 1.5,
"cmp_symbolic_indexed": 7.5,
"cmp_symbolic_register": 4.5,
"dint": 1.5,
"inc_indexed": 6.0,
"inc_register": 1.5,
"inc_symbolic": 6.0,
"incd_register": 1.5,
"incd_symbolic": 6.0,
"inv_register": 1.5,
"jc_symbolic": 3.0,
"jcc_symbolic": 3.0,
"jge_symbolic": 3.0,
"jl_symbolic": 3.0,
"jmp_symbolic": 3.0,
"jnc_symbolic": 3.0,
"jnz_symbolic": 3.0,
"jz_symbolic": 3.0,
"mov_RESHI_register": 1.5,
"mov_RESLO_register": 1.5,
"mov_absolute_absolute": 7.5,
"mov_absolute_indexed": 7.5,
"mov_absolute_register": 4.5,
"mov_autoincrement_indexed": 6.0,
"mov_autoincrement_register": 3.0,
"mov_immediate_absolute": 6.0,
"mov_immediate_indexed": 6.0,
"mov_immediate_register": 3.0,
"mov_immediate_symbolic": 6.0,
"mov_indexed_absolute": 7.5,
"mov_indexed_indexed": 7.5,
"mov_indexed_register": 4.5,
"mov_indirect_absolute": 6.0,
"mov_indirect_indexed": 6.0,
"mov_indirect_register": 3.0,
"mov_register_MPY": 1.5,
"mov_register_OP2": 1.5,
"mov_register_absolute": 4.5,
"mov_register_indexed": 4.5,
"mov_register_register": 1.5,
"mov_symbolic_absolute": 7.5,
"mov_symbolic_indexed": 7.5,
"mov_symbolic_register": 4.5,
"nop": 1.5,
"pop_register": 3.0,
"push_register": 4.5,
"ret": 1.5,
"reti": 1.5,
"rla_indexed": 6.0,
"rla_register": 1.5,
"rla_symbolic": 6.0,
"rlc_register": 1.5,
"rra_register": 1.5,
"rra_symbolic": 6.0,
"rrc_indexed": 6.0,
"rrc_register": 1.5,
"rrc_symbolic": 6.0,
"sub_absolute_register": 4.5,
"sub_immediate_register": 3.0,
"sub_indexed_indexed": 9.0,
"sub_indexed_register": 4.5,
"sub_register_indexed": 6.0,
"sub_register_register": 1.5,
"sub_symbolic_register": 4.5,
"subc_register_register": 1.5,
"swpb_register": 1.5,
"sxt_register": 1.5,
"xor_absolute_indexed": 9.0,
"xor_absolute_register": 4.5,
"xor_autoincrement_register": 3.0,
"xor_immediate_indexed": 7.5,
"xor_immediate_register": 3.0,
"xor_indexed_indexed": 9.0,
"xor_indexed_register": 4.5,
"xor_indirect_register": 3.0,
"xor_register_indexed": 6.0,
"xor_register_register": 1.5,
"xor_symbolic_indexed": 9.0,
"xor_symbolic_register": 4.5,
"zext_register": 1.5
}
}
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