Undivide MCLK and SMCLK in hw_init

[byeongjee]

hw_init programmed CSCTL1 (DCO frequency) but never CSCTL3, and a reset
returns CSCTL3 to 33h, which divides both MCLK and SMCLK by 8. The fresh-boot
path fixes this in timing_gpio_init, but a recovery boot jumps straight back
into the region without running it, so every resumed region ran at DCO/8 —
2 MHz in the default 16 MHz build.

hw_init now writes CSCTL3 = 0 inside the CSKEY window for every frequency.
The CSKEY unlock moved out of the F_CPU branches, and the 1 MHz build now
programs DCOFSEL_0 explicitly: it was only correct before because the reset
DCO (8 MHz) divided by 8 happens to be 1 MHz.

Measurements

ckpt bench milp crc --cap 10uF, 3 runs per configuration, execution time in
microseconds (result checksum 39423 in all runs):

halt mode	before	after
bor	336633 / 339032 / 339301	23567 / 23567 / 23567
swbor	10698 / 10698 / 10698	10640 / 10641 / 10641

BOR is the affected mode: it takes a real reset, so CSCTL3 came back divided.
SWBOR jumps to _start without a hardware reset, so the divider was never
reset there and the timing is unchanged, as expected.

uv run pytest tests/ -m "milp or rockclimb or schematic": 93 passed.