All issues

Search results

F2 small shell: place_design (Vivado 2025.2) drops a physical-only VCC tie on two locked static slices at ~1.3M-cell CL scale -> HDPRVerify-41, AFI ingestion rejected (deterministic, scale-triggered)

Status: Open.

#799 In aws/aws-fpga;

· NabilAziz99 opened on Jul 31, 2026

AWS F2 Vitis platform mismatch: device shell v10212415 but public platforms are v10162423/v03072517

Status: Open.

#795 In aws/aws-fpga;

· rishikakushwah16 opened on May 30, 2026

AWS F2 FPGA to FPGA low latency communication

Status: Open.

#791 In aws/aws-fpga;

· sarangzambare opened on Apr 28, 2026

Question: XDMA Driver Install Guide vs ERRATA

Status: Open.

#790 In aws/aws-fpga;

· BasharSi45 opened on Apr 22, 2026

C_TEST not working

Status: Open.

#781 In aws/aws-fpga;

· d1story opened on Mar 31, 2026

support for multiple queues in SPP driver

Status: Open.

#778 In aws/aws-fpga;

· chenv24 opened on Feb 19, 2026

Add Riviera-PRO support

Status: Open.

#770 In aws/aws-fpga;

· yarons opened on Jan 22, 2026

Support for Vitis AFI flow (create_vitis_afi.sh) on F2 instances for new projects

Status: Open.

#765 In aws/aws-fpga;

· yzhwang opened on Dec 19, 2025

How are we supposed to set the clock and timing constraints? We provide a detailed example worked out that contradicts the documentation and fails to allow configuring the clock and timing.

Status: Open.

#763 In aws/aws-fpga;

· dsw opened on Dec 1, 2025

Inconsistent "F2 Clock Recipe Tables"

Status: Open.

#761 In aws/aws-fpga;

· dsw opened on Nov 30, 2025

Documentation on clock tools seems to be inconsistent.

Status: Open.

#760 In aws/aws-fpga;

· dsw opened on Nov 30, 2025

vivado 2025.2 support

Status: Open.

#758 In aws/aws-fpga;

· pylaterreur opened on Nov 24, 2025