v2.3.0

.github/workflows/Pipeline.yml

@@ -3,6 +3,7 @@ name: Verify PoC and Generate Documentation
 on:
   push:
   pull_request:
+  workflow_dispatch:
 
 jobs:
   Prepare:

.sigasi/project.sigasi

@@ -0,0 +1,37 @@
+{
+    "name": "PoC",
+    "targets": {
+       "Generic": {
+						"environment": {
+							"BOARD":  "GENERIC",
+							"VENDOR": "GENERIC"
+						},
+            "command" : "cd temp && vsim -do ../regression.tcl",
+						"ignore": ["temp"]
+        },
+				"Altera": {
+						"environment": {
+							"BOARD":  "S2GXAV",
+							"VENDOR": "Altera"
+						},
+            "command" : "cd temp && vsim -do ../regression.tcl",
+						"ignore": ["temp"],
+						"dependencies": [{
+							"Quartus": [
+								"altera_mf"
+							]
+						}]
+        },
+				"Xilinx": {
+						"environment": {
+							"BOARD":  "KC705",
+							"VENDOR": "Xilinx"
+						},
+            "command" : "cd temp && vsim -do ../regression.tcl",
+						"ignore": ["temp"],
+            "dependencies": [
+                {"Vivado": {"version": "Vivado2025.2", "targets": ["unisim", "unimacro"] } }
+            ]
+        }
+    }
+}

docs/index.rst

@@ -62,6 +62,35 @@ shipped with a Python based infrastructure to offer a command line based fronten
 
    .. rubric:: News
 
+.. attention:: v3.0.0
+
+   .. rublic:: Planned Additions
+
+   * AXI4 multiplexer / demultiplexer
+   * AXI4-Lite multiplexer / demultiplexer
+
+   .. rublic:: Planned Changes
+
+   * Rename branch ``master`` to ``main```
+   * Restructure AXI4 subdirectories.
+   * Whitespace fixes.
+   * ``axi4lite_VersionRegister``
+
+     * Reworked memory layout
+     * Linux driver
+
+.. admonition:: v2.3.0
+
+   * New AXI4-Lite devices
+
+     * ``axi4lite_BlockRAMAdapter``
+     * ``axi4lite_DRPdapter``
+     * ``axi4lite_UART``
+     * ``axi4lite_HRClock``
+
+   * Documentation updates
+   * More OSVVM-based testcases
+
 .. admonition:: v2.2.0
 
    * Documentation updates

prj/TerosHDL/PileOfCores_TerosHDL.yml

@@ -1,7 +1,7 @@
 name: PileOfCores
 project_disk_path: ''
 project_type: genericProject
-toplevel: ../../src/bus/axi4/AXI4Lite/AXI4Lite_Register.vhdl
+toplevel: ../../src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl
 files:
   - name: ../../src/common/common.vhdl
     file_type: vhdlSource
@@ -1909,6 +1909,22 @@ files:
     logical_name: PoC
     is_manual: true
     source_type: none
+  - name: ../../src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl
+    file_type: vhdlSource
+    file_version: '2008'
+    is_include_file: false
+    include_path: ''
+    logical_name: PoC
+    is_manual: true
+    source_type: none
+  - name: ../../src/mem/mem_GitVersionRegister.pkg.vhdl
+    file_type: vhdlSource
+    file_version: '2008'
+    is_include_file: false
+    include_path: ''
+    logical_name: PoC
+    is_manual: true
+    source_type: none
 hooks:
   pre_build: []
   post_build: []

regression.tcl

@@ -1,10 +1,12 @@
 # =============================================================================
 # Authors:
-#   Jonas Schreiner, Stefan Unrein
+#   Jonas Schreiner
+#   Stefan Unrein
+#   Patrick Lehmann
 #
 # License:
 # =============================================================================
-# Copyright 2025-2025 The PoC-Library Authors
+# Copyright 2025-2026 The PoC-Library Authors
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -20,9 +22,20 @@
 # =============================================================================
 
 namespace eval ::poc {
-	variable myConfigFile  "../tb/common/my_config_GENERIC.vhdl"
+	proc getEnv {var {default ""}} {
+		if {[info exists ::env($var)]} {
+			return $::env($var)
+		}
+		return $default
+	}
+
+	variable vendorName [getEnv VENDOR "GENERIC"]
+	variable boardName  [getEnv BOARD  "GENERIC"]
+
+	variable myConfigFile  "../tb/common/my_config_$boardName.vhdl"
 	variable myProjectFile "../tb/common/my_project.vhdl"
-	variable vendor "GENERIC"; # GENERIC for vendor-less build; Xilinx, Altera,... for vendor specific build
+
+	variable vendor $vendorName; # GENERIC for vendor-less build; Xilinx, Altera,... for vendor specific build
 }
 
 source ../lib/OSVVM-Scripts/StartUp.tcl
@@ -31,22 +44,35 @@ source ../lib/OSVVM-Scripts/StartUp.tcl
 build ../lib/OsvvmLibraries.pro
 
 if {$::osvvm::ToolName eq "GHDL"} {
-    SetExtendedAnalyzeOptions  {-frelaxed -Wno-specs -Wno-elaboration}
-    SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding}
-}
+	SetExtendedAnalyzeOptions  {-frelaxed -Wno-specs -Wno-elaboration}
+	SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding}
 
-if {$::osvvm::ToolName eq "RiveraPRO"} {
-    SetExtendedSimulationOptions {-unbounderror}
-}
+} elseif {$::osvvm::ToolName eq "RivieraPRO"} {
+	set RivieraSimOptions {-unbounderror}
 
-if {$::osvvm::ToolName eq "NVC"} {
-    SetExtendedAnalyzeOptions {--relaxed}
+} elseif {$::osvvm::ToolName eq "NVC"} {
+	ExtendedAnalyzeOptions {--relaxed}
+
+} elseif {$::osvvm::ToolName eq "Sigasi"} {
+
+} else {
+	error [format {
+======================================
+Unknown simulator selected: %s
+
+Supported simulators:
+  - GHDL
+  - RivieraPRO
+  - NVC
+Other tools:
+  - Sigasi in VSCode
+======================================
+} $::osvvm::ToolName]
 }
 
 #set ::osvvm::AnalyzeErrorStopCount 1
 #set ::osvvm::SimulateErrorStopCount 1
 
-
 build ../src/PoC.pro
 
 #SetSaveWaves

src/bus/axi4/AXI4Lite/AXI4Lite_GitVersionRegister.vhdl

@@ -11,6 +11,12 @@
 -- This version register can be auto filled with constants from Git. Software
 -- can read from what revision a firmware (bitstream, PL code) was build.
 --
+-- The Version-out-Port is used to make all values accessible to the PL. This
+-- can be used by another interface than AXI4L, if necessary.
+-- If you dont need the UID field, use this to directly create a constant out of
+-- the mem-file:
+-- constant My_Version : T_VersionRegister := to_VersionRegister(MEM_PATH);
+--
 -- Use the pre-synthesis script from
 --     PoC/tools/git/preSynth_GitVersionRegister_Vivado.tcl
 -- to create a memory file with all necessary information. Add this file name to
@@ -62,14 +68,16 @@ entity AXI4Lite_GitVersionRegister is
 		Reset        : in  std_logic;
 
 		AXI4Lite_m2s : in  T_AXI4Lite_BUS_M2S;
-		AXI4Lite_s2m : out T_AXI4Lite_BUS_S2M
+		AXI4Lite_s2m : out T_AXI4Lite_BUS_S2M;
+
+		Version      : out T_VersionRegister
 	);
 end entity;
 
 
 architecture rtl of AXI4Lite_GitVersionRegister is
 	constant CONFIG      : T_AXI4_Register_Vector       := get_Version_Descriptor;
-	constant VersionData : T_SLVV_32(0 to C_Num_Version_Header - 1) := read_Version_from_mem(PROJECT_DIR & VERSION_FILE_NAME);
+	constant VersionData : T_SLVV_32(0 to C_Num_VersionHeader - 1) := read_Version_from_mem(PROJECT_DIR & VERSION_FILE_NAME);
 
 	signal   RegisterFile_ReadPort   : T_SLVV(0 to CONFIG'Length -1)(DATA_BITS - 1 downto 0);
 	signal   RegisterFile_WritePort  : T_SLVV(0 to CONFIG'Length -1)(DATA_BITS - 1 downto 0);
@@ -98,8 +106,9 @@ begin
 		RegisterFile_ReadPort   => RegisterFile_ReadPort,
 		RegisterFile_WritePort  => RegisterFile_WritePort
 	);
-	RegisterFile_WritePort(0 to C_Num_Version_Header -1) <= VersionData;
-	RegisterFile_WritePort(C_Num_Version_Header to C_Num_Version_Register -1) <= UID_vec;
+	RegisterFile_WritePort(0 to C_Num_VersionHeader -1) <= VersionData;
+	RegisterFile_WritePort(C_Num_VersionHeader to C_Num_VersionRegister -1) <= UID_vec;
+	Version <= to_VersionRegister(RegisterFile_ReadPort);
 
 	---------------------------------
 	-- Generate data for UID-vector