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Make CLR logic synchronous
rtlRegister Transfer Level hardware designRegister Transfer Level hardware designStatus: Open.#52 In TENNLab-UTK/fpga;Migrate from deprecated Edalize Tool API to the Flow API
good first issueGood for newcomersGood for newcomersStatus: Open.#51 In TENNLab-UTK/fpga;Remove references to Intel
documentationImprovements or additions to documentationImprovements or additions to documentationgood first issueGood for newcomersGood for newcomersStatus: Open.#45 In TENNLab-UTK/fpga;Testing CI
enhancementNew feature or requestNew feature or requestStatus: Open.#35 In TENNLab-UTK/fpga;Networks and Input Spike Rasters for Integration Testing
frameworkTENNLAB Framework interoperability or API complianceTENNLAB Framework interoperability or API compliancehelp wantedExtra attention is neededExtra attention is neededStatus: Open.#34 In TENNLab-UTK/fpga;Neurons without incoming synapses that are on a path from an input neuron are handled erroneously in hardware
bugSomething isn't workingSomething isn't workingdefer/delayImpeded or irrelevant due to other issueImpeded or irrelevant due to other issuertlRegister Transfer Level hardware designRegister Transfer Level hardware designStatus: Open.#33 In TENNLab-UTK/fpga;Multiple Networks on Processor
defer/delayImpeded or irrelevant due to other issueImpeded or irrelevant due to other issueframeworkTENNLAB Framework interoperability or API complianceTENNLAB Framework interoperability or API compliancertlRegister Transfer Level hardware designRegister Transfer Level hardware designStatus: Open.#9 In TENNLab-UTK/fpga;"Binary" or "Fire" Source Modes
enhancementNew feature or requestNew feature or requestrtlRegister Transfer Level hardware designRegister Transfer Level hardware designStatus: Open.#8 In TENNLab-UTK/fpga;Create distinction between targets and build hosts
enhancementNew feature or requestNew feature or requestStatus: Open.#2 In TENNLab-UTK/fpga;