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[ROCm] Route dense CP softmax-LSE correction through a native kernel - #708

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[ROCm] Route dense CP softmax-LSE correction through a native kernel#708
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zjin-lcf:issue-693-native-dense-lse-correction

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The context-parallel softmax-LSE merge (flash_attn_fwd_softmax_lse_correction and its second-half variant) ran through @jit_fuser / torch.compile on ROCm. Dynamo can hold more than one compiled variant of these functions, and on ROCm the variants disagree by ~1 ULP because libdevice.log1p contracts differently under different Triton launch configurations (issue #693). A reference model and an actor model built from the same checkpoint then diverge.

Add a fixed-configuration native kernel for the dense layout, mirroring the existing THD path:

  • nvte_cp_lse_correction C API + context_parallel::lse_correction kernel
  • tex.lse_correction PyTorch binding
  • route flash_attn_fwd_softmax_lse_correction and the second-half variant through the native kernel on ROCm (IS_HIP_EXTENSION), leaving the CUDA path unchanged

The native kernel returns identical bits for every launch configuration, so the merge is bitwise-reproducible. Add regression tests asserting bitwise stability of both correction functions across intervening shapes.

Fixes: #693

The context-parallel softmax-LSE merge (flash_attn_fwd_softmax_lse_correction
and its second-half variant) ran through @jit_fuser / torch.compile on ROCm.
Dynamo can hold more than one compiled variant of these functions, and on ROCm
the variants disagree by ~1 ULP because libdevice.log1p contracts differently
under different Triton launch configurations (issue ROCm#693). A reference model and
an actor model built from the same checkpoint then diverge.

Add a fixed-configuration native kernel for the dense layout, mirroring the
existing THD path:
  * nvte_cp_lse_correction C API + context_parallel::lse_correction kernel
  * tex.lse_correction PyTorch binding
  * route flash_attn_fwd_softmax_lse_correction and the second-half variant
    through the native kernel on ROCm (IS_HIP_EXTENSION), leaving the CUDA
    path unchanged

The native kernel returns identical bits for every launch configuration, so the
merge is bitwise-reproducible. Add regression tests asserting bitwise stability
of both correction functions across intervening shapes.

Fixes: ROCm#693
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CP LSE merge switches compiled variants on ROCm, breaking forward reproducibility

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