Computer Engineering @ University of Florida
RTL design · UVM verification · Embedded systems
Full portfolio — write-ups, architecture diagrams, and a live WebGL demo
I like the part of the stack where software stops being an abstraction — RTL, firmware, and the boards they run on. Most of what I build starts as a question about how something actually behaves under load, then turns into a testbench or a scope trace that answers it.
I care about designs that are provably correct, not just ones that pass a smoke test.
| Project | What it is |
|---|---|
| AXI4-Stream Packet FIFO | Store-and-forward RTL with a UVM environment that predicts every dropped frame exactly. 5/5 injected bugs caught by mutation testing. |
| RTOS Monitoring Node | Five-task FreeRTOS firmware on STM32F103 streaming telemetry to an MQTT gateway. 93+ host-side unit tests. |
| AutoCar SLAM | A robot car that maps a room while it drives. ROS 2, RPLIDAR, live Foxglove visualisation. |
| DE10-Nano OpenCL | ARM-to-FPGA acceleration on Cyclone V — BSP, MMD layer, driver, and host application. |
| APB UART Verification | Two-agent UVM environment closing 100% functional coverage on a 16550-compatible core. |
| The Beauty and Math | A parametric heart drawn from 2,500 particles of whatever you type. Runs in the browser. |
HDL & verification SystemVerilog · UVM 1.2 · VHDL · SVA · functional coverage Simulators & EDA Questa · Vivado XSim · VCS · Verilator · Quartus Prime · LTspice Embedded C/C++ · FreeRTOS · STM32 HAL · Pico SDK · ESP32 · CMake Protocols AXI4-Stream · APB · I²C · UART · SPI · ESP-NOW Systems Python · ROS 2 · Linux · Git · Altium
