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fix(SimTop): connext AXI in DUT when !isFPGA#888

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klin02 merged 1 commit into
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isFPGA
Jun 2, 2026
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fix(SimTop): connext AXI in DUT when !isFPGA#888
klin02 merged 1 commit into
masterfrom
isFPGA

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@klin02 klin02 commented Jun 2, 2026

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@klin02 klin02 requested a review from poemonsense June 2, 2026 13:04
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klin02 commented Jun 2, 2026

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DUT will connect AXI inside by default, and override the connection when isFPGA:
OSCPU/NutShell#259

@klin02 klin02 merged commit 261b441 into master Jun 2, 2026
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@klin02 klin02 deleted the isFPGA branch June 2, 2026 15:32
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Current result (nutshell) - 2026-06-03 00:28

Instance Module Total LUTs Logic LUTs LUTRAMs SRLs FFs RAMB36 RAMB18 URAM DSP Blocks
U_CPU_TOP SimTop_wrapper 31084 (0.8%) 30019 1064 1 47211 17 13 4 16
nutcore NutCore 15153 (0.4%) 14992 160 1 20612 17 9 0 16
difftest_host HostEndpoint 1258 (0.0%) 686 572 0 2416 0 0 0 0
endpoint GatewayEndpoint 11381 (0.3%) 11381 0 0 20467 0 0 0 0

Archive (latest, 20260602)

Instance Module Total LUTs Logic LUTs LUTRAMs SRLs FFs RAMB36 RAMB18 URAM DSP Blocks
U_CPU_TOP SimTop_wrapper 31084 (0.8%) 30019 1064 1 47211 17 13 4 16
nutcore NutCore 15153 (0.4%) 14992 160 1 20612 17 9 0 16
difftest_host HostEndpoint 1258 (0.0%) 686 572 0 2416 0 0 0 0
endpoint GatewayEndpoint 11381 (0.3%) 11381 0 0 20467 0 0 0 0

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