refactor: remove HuanCun and tl2tl CoupledL2 from XSCache

.github/workflows/main.yml

@@ -27,8 +27,6 @@ jobs:
           fetch-depth: '0'
       - name: check rocket-chip
         run: cd rocket-chip && git fetch --all && git merge-base --is-ancestor `git rev-parse HEAD` origin/master
-      - name: check HuanCun
-        run: cd HuanCun && git fetch --all && git merge-base --is-ancestor `git rev-parse HEAD` origin/master
       - name: check utility
         run: cd utility && git fetch --all && git merge-base --is-ancestor `git rev-parse HEAD` origin/master
 
@@ -87,15 +85,14 @@ jobs:
       run: tar -zcf ${{ env.VERILATOR_ARCHIVE }} verilator
 
   # This workflow contains a single job called "build"
-  tl-test_L2:
+  chi-test_L2:
     # The type of runner that the job will run on
     runs-on: ubuntu-22.04
 
     # Environments
     env:
-      RUN_ARCHIVE: coupledL2-tl-test-new-run-${{ github.sha }}
-      RUN_ARCHIVE_TL: coupledL2-tl-test-new-run-${{ github.sha }}-tilelink.tar.gz
-      RUN_ARCHIVE_CHI: coupledL2-tl-test-new-run-${{ github.sha }}-chi.tar.gz
+      RUN_ARCHIVE: xscache-chi-test-run-${{ github.sha }}
+      RUN_ARCHIVE_CHI: xscache-chi-test-run-${{ github.sha }}.tar.gz
       VERILATOR_ARCHIVE: verilator-ubuntu-22.04-clang-17.tar.gz
 
     # Steps represent a sequence of tasks that will be executed as part of the job
@@ -187,24 +184,6 @@ jobs:
             test -d ./tl-test-new/run || mkdir -p ./tl-test-new/run
             tar -zcf ${{ env.RUN_ARCHIVE_CHI }} ./tl-test-new/run
 
-      # Clean artifacts folder (./tl-test-new/run) after successful run
-      - name: Unit Test for TileLink version
-        run: |
-            rm -rf tl-test-new
-            git clone https://github.com/OpenXiangShan/tl-test-new
-            cd ./tl-test-new
-            git checkout ${{ env.TL_TEST_NEW_COMMIT }}
-            sed -i 's/ari.target.*/ari.target = 240/g' ./configs/user.tltest.ini
-            rm -rf ./dut/XSCache && ln -s ../.. ./dut/XSCache
-            make coupledL2-test-l2l3l2 run THREADS_BUILD=4 CXX_COMPILER=clang++-17
-            rm -rf run/*.vcd run/*.fst run/*.log run/*.db
-
-      - name: Tar up artifacts of Unit Test for TileLink version
-        if: always()
-        run: |
-            test -d ./tl-test-new/run || mkdir -p ./tl-test-new/run
-            tar -zcf ${{ env.RUN_ARCHIVE_TL }} ./tl-test-new/run
-
       - name: Upload artifacts of Unit Test
         if: always()
         uses: actions/upload-artifact@v4

.gitmodules

@@ -4,9 +4,6 @@
 [submodule "utility"]
 	path = utility
 	url = https://github.com/OpenXiangShan/utility
-[submodule "HuanCun"]
-	path = HuanCun
-	url = https://github.com/OpenXiangShan/HuanCun.git
 [submodule "OpenNCB"]
 	path = OpenNCB
 	url = https://github.com/OpenXiangShan/OpenNCB.git

Makefile

@@ -34,27 +34,12 @@ MEM_GEN = ./scripts/vlsi_mem_gen
 MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
 
 gen-test-top:
-	mill -i XSCache.test.runMain coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR_L2) --target systemverilog --split-verilog
-	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V_L2).conf" "$(BUILD_DIR_L2)"
+	mill -i XSCache.test.runMain xscache.coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR_L2) --target systemverilog --split-verilog
+	if [ -f "$(TOP_V_L2).conf" ]; then $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V_L2).conf" "$(BUILD_DIR_L2)"; fi
 
 gen-test-top-chi:
-	mill -i XSCache.test.runMain coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR_L2) $(CHI_TOP_ARGS) --target systemverilog --split-verilog
-	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V_L2).conf" "$(BUILD_DIR_L2)"
-
-test-top-l2:
-	$(MAKE) gen-test-top SYSTEM=L2
-
-test-top-l2standalone:
-	$(MAKE) gen-test-top SYSTEM=L2_Standalone
-
-test-top-l2l3-huancun:
-	$(MAKE) gen-test-top SYSTEM=L2L3
-
-test-top-l2l3l2-huancun:
-	$(MAKE) gen-test-top SYSTEM=L2L3L2
-
-test-top-fullsys-huancun:
-	$(MAKE) gen-test-top SYSTEM=fullSys
+	mill -i XSCache.test.runMain xscache.coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR_L2) $(CHI_TOP_ARGS) --target systemverilog --split-verilog
+	if [ -f "$(TOP_V_L2).conf" ]; then $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V_L2).conf" "$(BUILD_DIR_L2)"; fi
 
 test-top-chi:
 	$(MAKE) gen-test-top-chi SYSTEM=CHIL2 $(CHI_PASS_ARGS)
@@ -72,13 +57,13 @@ test-top-chi-quadcore-2ul:
 	$(MAKE) gen-test-top-chi SYSTEM=CHIL2 $(CHI_PASS_ARGS) NUM_CORE=4 NUM_TL_UL=2
 
 test-top-l3-openllc:
-	mill -i XSCache.test.runMain openLLC.TestTop_L3 -td build --target systemverilog --split-verilog
+	mill -i XSCache.test.runMain xscache.openLLC.TestTop_L3 -td build --target systemverilog --split-verilog
 
 test-top-l2l3-openllc:
-	mill -i XSCache.test.runMain openLLC.TestTopSoC_SingleCore -td $(BUILD_DIR_LLC) --target systemverilog --split-verilog
+	mill -i XSCache.test.runMain xscache.openLLC.TestTopSoC_SingleCore -td $(BUILD_DIR_LLC) --target systemverilog --split-verilog
 
 test-top-l2l3l2-openllc:
-	mill -i XSCache.test.runMain openLLC.TestTopSoC_DualCore -td $(BUILD_DIR_LLC) --target systemverilog --split-verilog
+	mill -i XSCache.test.runMain xscache.openLLC.TestTopSoC_DualCore -td $(BUILD_DIR_LLC) --target systemverilog --split-verilog
 
 clean:
 	rm -rf ./build
@@ -95,4 +80,4 @@ reformat:
 checkformat:
 	mill -i __.checkFormat
 
-.PHONY: init bsp checkformat clean compile-coupledl2 compile-openllc idea reformat 
+.PHONY: init bsp checkformat clean compile-coupledl2 compile-openllc idea reformat 

README.md

@@ -1,11 +1,18 @@
-# CoupledL2
+# XSCache
 
-![Build Status](https://github.com/RISCVERS/HuanCun/actions/workflows/main.yml/badge.svg)
+CHI-only cache subsystem built from `CoupledL2 (tl2chi)` and `OpenLLC`.
 
 ## Compile source code
 
-```
+``` 
 make init
 make compile
 ```
 
+## Generate CHI test tops
+
+``` 
+make test-top-chi
+make test-top-l2l3-openllc
+make test-top-l2l3l2-openllc
+```

build.sc

@@ -81,13 +81,6 @@ object utility extends HasChisel {
   )
 }
 
-object huancun extends HasChisel {
-  override def millSourcePath = pwd / "HuanCun"
-  override def moduleDeps = super.moduleDeps ++ Seq(
-    rocketchip, utility
-  )
-}
-
 object openNCB extends HasChisel {
   override def millSourcePath = pwd / "OpenNCB"
   override def moduleDeps = super.moduleDeps ++ Seq(rocketchip)
@@ -101,12 +94,10 @@ object XSCache extends HasChisel with $file.common.XSCacheModule {
 
   def utilityModule: ScalaModule = utility
 
-  def huancunModule: ScalaModule = huancun
-
   def openNCBModule: ScalaModule = openNCB
 
   object test extends SbtTests with TestModule.ScalaTest
 
   override def scalacOptions = super.scalacOptions() ++ Agg("-deprecation", "-feature")
 
-}
+}

common.sc

@@ -7,9 +7,7 @@ trait XSCacheModule extends ScalaModule {
 
   def utilityModule: ScalaModule
 
-  def huancunModule: ScalaModule
-
   def openNCBModule: ScalaModule
 
-  override def moduleDeps = super.moduleDeps ++ Seq(rocketModule, utilityModule, huancunModule, openNCBModule)
-}
+  override def moduleDeps = super.moduleDeps ++ Seq(rocketModule, utilityModule, openNCBModule)
+}

src/main/scala/coupledL2/BaseSlice.scala

@@ -15,14 +15,14 @@
   * *************************************************************************************
   */
 
-package coupledL2
+package xscache.coupledL2
 
 import chisel3._
 import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink.TLBundle
 import utility._
-import coupledL2.prefetch._
+import xscache.coupledL2.prefetch._
 
 trait BaseOuterBundle
 

src/main/scala/coupledL2/tl2chi/Bundle.scala → src/main/scala/coupledL2/Bundle.scala

@@ -15,20 +15,15 @@
   * *************************************************************************************
   */
 
-package coupledL2.tl2chi
+package xscache.coupledL2
 
 import chisel3._
 import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink.TLPermissions._
 import utility.MemReqSource
-import coupledL2.{HasTLChannelBits, DirResult, PipeStatus}
-
-object CHIChannel {
-  def TXREQ = "b001".U
-  def TXRSP = "b010".U
-  def TXDAT = "b100".U
-}
+import xscache.coupledL2.{HasTLChannelBits, DirResult, PipeStatus}
+import xscache.chi.HasCHIOpcodes
 
 trait HasCHIChannelBits { this: Bundle =>
   val txChannel = UInt(3.W)
@@ -42,10 +37,10 @@ class PipeStatusWithCHI(implicit p: Parameters) extends PipeStatus
   val mshrTask = Bool()
 }
 
-class PCrdQueryBundle(implicit p: Parameters) extends TL2CHIL2Bundle with HasCHIOpcodes {
+class PCrdQueryBundle(implicit p: Parameters) extends CoupledL2Bundle with HasCHIOpcodes {
   val query = Output(ValidIO(new Bundle() {
     val pCrdType = UInt(PCRDTYPE_WIDTH.W)
     val srcID = UInt(SRCID_WIDTH.W)
   }))
   val grant = Input(Bool())
-}
+}

src/main/scala/coupledL2/Common.scala

@@ -15,14 +15,14 @@
   * *************************************************************************************
   */
 
-package coupledL2
+package xscache.coupledL2
 
 import chisel3._
 import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink.TLPermissions._
 import utility.MemReqSource
-import tl2chi.{HasCHIMsgParameters, HasCHIChannelBits, CHIREQ, MemAttr, OrderEncodings, MPAM}
+import xscache.chi.{CHIREQ, HasCHIMsgParameters, MemAttr, MPAM, OrderEncodings}
 
 abstract class L2Module(implicit val p: Parameters) extends Module with HasCoupledL2Parameters
 abstract class L2Bundle(implicit val p: Parameters) extends Bundle with HasCoupledL2Parameters
@@ -91,7 +91,6 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle
                                           // If true, MSHR should send an ack to L2 prefetcher.
   val needHint = prefetchOpt.map(_ => Bool())
 
-  // For DirtyKey in Release
   val dirty = Bool()
 
   // if this is an mshr task and it needs to write dir

src/main/scala/coupledL2/Consts.scala

@@ -17,7 +17,7 @@
 
 // See LICENSE.SiFive for license details.
 
-package coupledL2
+package xscache.coupledL2
 
 import chisel3._
 import chisel3.util._