feat, submodule, test: support TestTop for CoupledL2 + ZhuJiang

.github/workflows/main.yml

@@ -6,9 +6,9 @@ name: CI
 on:
   # Triggers the workflow on push or pull request events but only for the main branch
   push:
-    branches: [ master, chi-coupledl2 ]
+    branches: [ master ]
   pull_request:
-    branches: [ master, chi-coupledl2 ]
+    branches: [ master ]
 
   # Allows you to run this workflow manually from the Actions tab
   workflow_dispatch:
@@ -85,14 +85,15 @@ jobs:
       run: tar -zcf ${{ env.VERILATOR_ARCHIVE }} verilator
 
   # This workflow contains a single job called "build"
-  chi-test_L2:
+  unit-test:
     # The type of runner that the job will run on
     runs-on: ubuntu-22.04
 
     # Environments
     env:
-      RUN_ARCHIVE: xscache-chi-test-run-${{ github.sha }}
-      RUN_ARCHIVE_CHI: xscache-chi-test-run-${{ github.sha }}.tar.gz
+      RUN_ARCHIVE: xscache-test-run-${{ github.sha }}
+      RUN_ARCHIVE_OPENLLC: xscache-test-run-${{ github.sha }}-openllc.tar.gz
+      RUN_ARCHIVE_ZHUJIANG: xscache-test-run-${{ github.sha }}-zhujiang.tar.gz
       VERILATOR_ARCHIVE: verilator-ubuntu-22.04-clang-17.tar.gz
 
     # Steps represent a sequence of tasks that will be executed as part of the job
@@ -163,7 +164,7 @@ jobs:
           fi
 
       # Clean artifacts folder (./tl-test-new/run) after successful run
-      - name: Unit test for CHI version
+      - name: Unit test for CoupledL2 + OpenLLC
         run: |
             rm -rf tl-test-new
             git clone https://github.com/OpenXiangShan/tl-test-new
@@ -177,12 +178,32 @@ jobs:
             rm -rf ./dut/XSCache && ln -s ../.. ./dut/XSCache
             make openLLC-test-l2l3l2 run THREADS_BUILD=4 CXX_COMPILER=clang++-17
             rm -rf run/*.vcd run/*.fst run/*.log run/*.db
+
+      - name: Tar up artifacts of Unit Test for CoupledL2 + OpenLLC
+        if: always()
+        run: |
+            test -d ./tl-test-new/run || mkdir -p ./tl-test-new/run
+            tar -zcf ${{ env.RUN_ARCHIVE_OPENLLC }} ./tl-test-new/run
+
+      - name: Unit test for CoupledL2 + ZhuJiang
+        run: |
+            rm -rf tl-test-new
+            git clone --branch feat-zhujiang --single-branch https://github.com/OpenXiangShan/tl-test-new
+            cd ./tl-test-new
+            sed -i 's/ari.target.*/ari.target = 100/g' ./configs/user.tltest.ini
+            sed -i 's/cmo.enable .*=.*/cmo.enable = 1/g' ./configs/user.tltest.ini
+            sed -i 's/cmo.enable.cbo.clean.*=.*/cmo.enable.cbo.clean = 1/g' ./configs/user.tltest.ini
+            sed -i 's/cmo.enable.cbo.flush.*=.*/cmo.enable.cbo.flush = 1/g' ./configs/user.tltest.ini
+            sed -i 's/cmo.enable.cbo.inval.*=.*/cmo.enable.cbo.inval = 1/g' ./configs/user.tltest.ini
+            rm -rf ./dut/XSCache && ln -s ../.. ./dut/XSCache
+            make zhujiang-test-l2l3l2 run THREADS_BUILD=4 CXX_COMPILER=clang++-17
+            rm -rf run/*.vcd run/*.fst run/*.log run/*.db
 
-      - name: Tar up artifacts of Unit Test for CHI version
+      - name: Tar up artifacts of Unit Test for CoupledL2 + ZhuJiang
         if: always()
         run: |
             test -d ./tl-test-new/run || mkdir -p ./tl-test-new/run
-            tar -zcf ${{ env.RUN_ARCHIVE_CHI }} ./tl-test-new/run
+            tar -zcf ${{ env.RUN_ARCHIVE_ZHUJIANG }} ./tl-test-new/run
 
       - name: Upload artifacts of Unit Test
         if: always()

.gitmodules

@@ -7,3 +7,6 @@
 [submodule "OpenNCB"]
 	path = OpenNCB
 	url = https://github.com/OpenXiangShan/OpenNCB.git
+[submodule "ZhuJiang"]
+	path = ZhuJiang
+	url = https://github.com/OpenXiangShan/ZhuJiang.git

Makefile

@@ -28,17 +28,19 @@ CHI_TOP_ARGS = --issue $(ISSUE) --core $(NUM_CORE) --tl-ul $(NUM_TL_UL) --bank $
 		       --fpga $(FPGA)
 BUILD_DIR_L2 = ./build/coupledl2
 BUILD_DIR_LLC = ./build/openllc
+BUILD_DIR_ZJ_SINGLECORE = ./build/zj_singlecore
+BUILD_DIR_ZJ_DUALCORE = ./build/zj_dualcore
 TOP_V_L2 = $(BUILD_DIR_L2)/$(TOP).sv
 TOP_V_LLC = $(BUILD_DIR_LLC)/$(TOP).sv
 MEM_GEN = ./scripts/vlsi_mem_gen
 MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
 
 gen-test-top:
-	mill -i XSCache.test.runMain xscache.coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR_L2) --target systemverilog --split-verilog
+	mill -i XSCache.testtop.l2.runMain xscache.coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR_L2) --target systemverilog --split-verilog
 	if [ -f "$(TOP_V_L2).conf" ]; then $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V_L2).conf" "$(BUILD_DIR_L2)"; fi
 
 gen-test-top-chi:
-	mill -i XSCache.test.runMain xscache.coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR_L2) $(CHI_TOP_ARGS) --target systemverilog --split-verilog
+	mill -i XSCache.testtop.l2.runMain xscache.coupledL2.$(TOP)_$(SYSTEM) -td $(BUILD_DIR_L2) $(CHI_TOP_ARGS) --target systemverilog --split-verilog
 	if [ -f "$(TOP_V_L2).conf" ]; then $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V_L2).conf" "$(BUILD_DIR_L2)"; fi
 
 test-top-chi:
@@ -57,13 +59,19 @@ test-top-chi-quadcore-2ul:
 	$(MAKE) gen-test-top-chi SYSTEM=CHIL2 $(CHI_PASS_ARGS) NUM_CORE=4 NUM_TL_UL=2
 
 test-top-l3-openllc:
-	mill -i XSCache.test.runMain xscache.openLLC.TestTop_L3 -td build --target systemverilog --split-verilog
+	mill -i XSCache.testtop.openllc.runMain xscache.openLLC.TestTop_L3 -td build --target systemverilog --split-verilog
 
 test-top-l2l3-openllc:
-	mill -i XSCache.test.runMain xscache.openLLC.TestTopSoC_SingleCore -td $(BUILD_DIR_LLC) --target systemverilog --split-verilog
+	mill -i XSCache.testtop.openllc.runMain xscache.openLLC.TestTopOpenLLC_SingleCore -td $(BUILD_DIR_LLC) --target systemverilog --split-verilog
 
 test-top-l2l3l2-openllc:
-	mill -i XSCache.test.runMain xscache.openLLC.TestTopSoC_DualCore -td $(BUILD_DIR_LLC) --target systemverilog --split-verilog
+	mill -i XSCache.testtop.openllc.runMain xscache.openLLC.TestTopOpenLLC_DualCore -td $(BUILD_DIR_LLC) --target systemverilog --split-verilog
+
+test-top-zhujiang-singlecore:
+	mill -i XSCache.testtop.zhujiang.runMain zhujiang.TestTopZhuJiang_SingleCore -td $(BUILD_DIR_ZJ_SINGLECORE) --target systemverilog --split-verilog
+
+test-top-zhujiang-dualcore:
+	mill -i XSCache.testtop.zhujiang.runMain zhujiang.TestTopZhuJiang_DualCore -td $(BUILD_DIR_ZJ_DUALCORE) --target systemverilog --split-verilog
 
 clean:
 	rm -rf ./build

build.sc

@@ -96,8 +96,59 @@ object XSCache extends HasChisel with $file.common.XSCacheModule {
 
   def openNCBModule: ScalaModule = openNCB
 
-  object test extends SbtTests with TestModule.ScalaTest
+  object test extends SbtTests with TestModule.ScalaTest {
+    override def sources = T.sources {
+      Seq(
+        PathRef(pwd / "src" / "test" / "scala" / "ReplacementPolicyTest.scala"),
+        PathRef(pwd / "src" / "test" / "scala" / "TestSplittedSRAM.scala")
+      )
+    }
+  }
+
+  object testtop extends Module {
+    object l2 extends HasChisel {
+      override def millSourcePath = pwd
+      override def moduleDeps = super.moduleDeps ++ Seq(XSCache)
+      override def sources = T.sources {
+        Seq(PathRef(pwd / "src" / "test" / "scala" / "TestTopL2.scala"))
+      }
+      override def scalacOptions = super.scalacOptions() ++ Agg("-deprecation", "-feature")
+    }
+
+    object openllc extends HasChisel {
+      override def millSourcePath = pwd
+      override def moduleDeps = super.moduleDeps ++ Seq(XSCache)
+      override def sources = T.sources {
+        Seq(PathRef(pwd / "src" / "test" / "scala" / "TestTopOpenLLC.scala"))
+      }
+      override def scalacOptions = super.scalacOptions() ++ Agg("-deprecation", "-feature")
+    }
+
+    object zhujiang extends HasChisel {
+      override def millSourcePath = pwd
+      override def moduleDeps = super.moduleDeps ++ Seq(XSCache, zhujiangCompat)
+      override def sources = T.sources {
+        Seq(
+          PathRef(pwd / "src" / "test" / "scala" / "ZhuJiangBridge.scala"),
+          PathRef(pwd / "src" / "test" / "scala" / "TestTopZhuJiang.scala")
+        )
+      }
+      override def scalacOptions = super.scalacOptions() ++ Agg("-deprecation", "-feature")
+    }
+  }
 
   override def scalacOptions = super.scalacOptions() ++ Agg("-deprecation", "-feature")
 
 }
+
+object zhujiangCompat extends HasChisel {
+  override def millSourcePath = pwd / "ZhuJiang"
+  override def moduleDeps = super.moduleDeps ++ Seq(rocketchip, utility)
+  override def sources = T.sources {
+    Seq(
+      PathRef(millSourcePath / "src" / "main" / "scala"),
+      PathRef(millSourcePath / "xs-utils" / "src" / "main" / "scala")
+    )
+  }
+  override def scalacOptions = super.scalacOptions() ++ Agg("-deprecation", "-feature")
+}

src/main/scala/coupledL2/CoupledL2.scala

@@ -386,7 +386,8 @@ class CoupledL2(implicit p: Parameters) extends LazyModule with HasCoupledL2Para
       val l2FlushDone = Option.when(cacheParams.enableL2Flush) (Output(Bool()))
       val dft = Option.when(cacheParams.hasDFT)(Input(new SramBroadcastBundle))
       val dft_reset = Option.when(cacheParams.hasMbist)(Input(new DFTResetSignals()))
-      val chi = new PortIO
+      val lcreditCHI = Option.when(!p(EnableL2DecoupledDownstreamCHI))(new PortIO)
+      val decoupledCHI = Option.when(p(EnableL2DecoupledDownstreamCHI))(new DecoupledPortIO)
       val nodeID = Input(UInt())
       val cpu_wfi = Option.when(cacheParams.enableL2Flush)(Input(Bool()))
     })
@@ -403,15 +404,23 @@ class CoupledL2(implicit p: Parameters) extends LazyModule with HasCoupledL2Para
     print_bundle_fields(node.in.head._2.bundle.requestFields, "usr")
     print_bundle_fields(node.in.head._2.bundle.echoFields, "echo")
 
-    require(io.chi.tx.rsp.getWidth == io.chi.rx.rsp.getWidth)
-    require(io.chi.tx.dat.getWidth == io.chi.rx.dat.getWidth)
-
     println(s"CHI Issue Version: ${p(CHIIssue)}")
-    println(s"CHI REQ Flit Width: ${io.chi.tx.req.flit.getWidth}")
-    println(s"CHI RSP Flit Width: ${io.chi.tx.rsp.flit.getWidth}")
-    println(s"CHI SNP Flit Width: ${io.chi.rx.snp.flit.getWidth}")
-    println(s"CHI DAT Flit Width: ${io.chi.rx.dat.flit.getWidth}")
-    println(s"CHI Port Width: ${io.chi.getWidth}")
+    io.lcreditCHI.foreach { chi =>
+      require(chi.tx.rsp.getWidth == chi.rx.rsp.getWidth)
+      require(chi.tx.dat.getWidth == chi.rx.dat.getWidth)
+      println(s"CHI REQ Flit Width: ${chi.tx.req.flit.getWidth}")
+      println(s"CHI RSP Flit Width: ${chi.tx.rsp.flit.getWidth}")
+      println(s"CHI SNP Flit Width: ${chi.rx.snp.flit.getWidth}")
+      println(s"CHI DAT Flit Width: ${chi.rx.dat.flit.getWidth}")
+      println(s"CHI Port Width: ${chi.getWidth}")
+    }
+    io.decoupledCHI.foreach { chi =>
+      println(s"Decoupled CHI REQ Flit Width: ${chi.tx.req.bits.getWidth}")
+      println(s"Decoupled CHI RSP Flit Width: ${chi.tx.rsp.bits.getWidth}")
+      println(s"Decoupled CHI SNP Flit Width: ${chi.rx.snp.bits.getWidth}")
+      println(s"Decoupled CHI DAT Flit Width: ${chi.rx.dat.bits.getWidth}")
+      println(s"Decoupled CHI Port Width: ${chi.getWidth}")
+    }
 
     println(s"Cacheable:")
     node.edges.in.headOption.foreach { n =>
@@ -685,19 +694,28 @@ class CoupledL2(implicit p: Parameters) extends LazyModule with HasCoupledL2Para
       Cat(slices.zipWithIndex.map { case (s, i) => s.io.out.rx.dat.ready && rxdatSliceID === i.U }).orR
     )
 
-    val linkMonitor = Module(new LinkMonitor)
-    val rxdatPipe = Pipeline(linkMonitor.io.in.rx.dat)
-    val rxrspPipe = Pipeline(linkMonitor.io.in.rx.rsp)
-    linkMonitor.io.in.tx.req <> txreq
-    linkMonitor.io.in.tx.rsp <> txrsp
-    linkMonitor.io.in.tx.dat <> txdat
-    rxsnp <> linkMonitor.io.in.rx.snp
-    rxrsp <> rxrspPipe
-    rxdat <> rxdatPipe
-    io.chi <> linkMonitor.io.out
-    linkMonitor.io.nodeID := io.nodeID
-    linkMonitor.io.exitco.foreach { _ :=
-      Cat(slices.zipWithIndex.map { case (s, i) => s.io.l2FlushDone.getOrElse(false.B)}).andR && io.cpu_wfi.getOrElse(false.B)
+    if (p(EnableL2DecoupledDownstreamCHI)) {
+      io.decoupledCHI.get.tx.req <> txreq
+      io.decoupledCHI.get.tx.rsp <> txrsp
+      io.decoupledCHI.get.tx.dat <> txdat
+      rxsnp <> io.decoupledCHI.get.rx.snp
+      rxrsp <> Pipeline(io.decoupledCHI.get.rx.rsp)
+      rxdat <> Pipeline(io.decoupledCHI.get.rx.dat)
+    } else {
+      val linkMonitor = Module(new LinkMonitor)
+      val rxdatPipe = Pipeline(linkMonitor.io.in.rx.dat)
+      val rxrspPipe = Pipeline(linkMonitor.io.in.rx.rsp)
+      linkMonitor.io.in.tx.req <> txreq
+      linkMonitor.io.in.tx.rsp <> txrsp
+      linkMonitor.io.in.tx.dat <> txdat
+      rxsnp <> linkMonitor.io.in.rx.snp
+      rxrsp <> rxrspPipe
+      rxdat <> rxdatPipe
+      io.lcreditCHI.get <> linkMonitor.io.out
+      linkMonitor.io.nodeID := io.nodeID
+      linkMonitor.io.exitco.foreach { _ :=
+        Cat(slices.zipWithIndex.map { case (s, i) => s.io.l2FlushDone.getOrElse(false.B)}).andR && io.cpu_wfi.getOrElse(false.B)
+      }
     }
 
     XSPerfAccumulate("pcrd_count", pCrdQueue_s2.io.enq.fire)

src/main/scala/coupledL2/L2Param.scala

@@ -28,6 +28,7 @@ import utility.{Code, MemReqSource, ReqSourceKey}
 import xscache.common.{AliasKey, CacheParameters, IsHitKey, PrefetchKey, BankBitsKey}
 
 case object EnableL2ClockGate extends Field[Boolean](true)
+case object EnableL2DecoupledDownstreamCHI extends Field[Boolean](false)
 
 // L1 Cache Params, used for TestTop generation
 case class L1Param

src/test/scala/chi/TestTop.scala → src/test/scala/TestTopL2.scala

@@ -181,17 +181,17 @@ class TestTop_CHIL2(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, ext
           clock = l2.module.clock,
           reset = l2.module.reset,
           rnId  = l2.module.io.nodeID,
-          txreqflit = l2.module.io.chi.tx.req.flit, txreqflitv = l2.module.io.chi.tx.req.flitv,
-          rxrspflit = l2.module.io.chi.rx.rsp.flit, rxrspflitv = l2.module.io.chi.rx.rsp.flitv,
-          rxdatflit = l2.module.io.chi.rx.dat.flit, rxdatflitv = l2.module.io.chi.rx.dat.flitv,
-          rxsnpflit = l2.module.io.chi.rx.snp.flit, rxsnpflitv = l2.module.io.chi.rx.snp.flitv,
-          txrspflit = l2.module.io.chi.tx.rsp.flit, txrspflitv = l2.module.io.chi.tx.rsp.flitv,
-          txdatflit = l2.module.io.chi.tx.dat.flit, txdatflitv = l2.module.io.chi.tx.dat.flitv,
+          txreqflit = l2.module.io.lcreditCHI.get.tx.req.flit, txreqflitv = l2.module.io.lcreditCHI.get.tx.req.flitv,
+          rxrspflit = l2.module.io.lcreditCHI.get.rx.rsp.flit, rxrspflitv = l2.module.io.lcreditCHI.get.rx.rsp.flitv,
+          rxdatflit = l2.module.io.lcreditCHI.get.rx.dat.flit, rxdatflitv = l2.module.io.lcreditCHI.get.rx.dat.flitv,
+          rxsnpflit = l2.module.io.lcreditCHI.get.rx.snp.flit, rxsnpflitv = l2.module.io.lcreditCHI.get.rx.snp.flitv,
+          txrspflit = l2.module.io.lcreditCHI.get.tx.rsp.flit, txrspflitv = l2.module.io.lcreditCHI.get.tx.rsp.flitv,
+          txdatflit = l2.module.io.lcreditCHI.get.tx.dat.flit, txdatflitv = l2.module.io.lcreditCHI.get.tx.dat.flitv,
           time = time_sim, timev = extTime.B
         )
       }
 
-      l2.module.io.chi <> io(i).chi
+      l2.module.io.lcreditCHI.get <> io(i).chi
 
       l2.module.io.l2_hint <> io_l1(i).l2Hint
 

src/test/scala/TestTop_LLC.scala → src/test/scala/TestTopOpenLLC.scala

@@ -60,7 +60,7 @@ object TestTop_L3 extends App {
   ))
 }
 
-class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: String = Issue.Eb, extTime: Boolean = true)(implicit p: Parameters) extends LazyModule
+class TestTopOpenLLC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue: String = Issue.Eb, extTime: Boolean = true)(implicit p: Parameters) extends LazyModule
   with HasCHIMsgParameters {
 
   /*   L1D(L1I)* L1D(L1I)* ... L1D(L1I)*
@@ -270,17 +270,17 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue:
           clock = l2.module.clock,
           reset = l2.module.reset,
           rnId  = l2.module.io.nodeID,
-          txreqflit = l2.module.io.chi.tx.req.flit, txreqflitv = l2.module.io.chi.tx.req.flitv,
-          rxrspflit = l2.module.io.chi.rx.rsp.flit, rxrspflitv = l2.module.io.chi.rx.rsp.flitv,
-          rxdatflit = l2.module.io.chi.rx.dat.flit, rxdatflitv = l2.module.io.chi.rx.dat.flitv,
-          rxsnpflit = l2.module.io.chi.rx.snp.flit, rxsnpflitv = l2.module.io.chi.rx.snp.flitv,
-          txrspflit = l2.module.io.chi.tx.rsp.flit, txrspflitv = l2.module.io.chi.tx.rsp.flitv,
-          txdatflit = l2.module.io.chi.tx.dat.flit, txdatflitv = l2.module.io.chi.tx.dat.flitv,
+          txreqflit = l2.module.io.lcreditCHI.get.tx.req.flit, txreqflitv = l2.module.io.lcreditCHI.get.tx.req.flitv,
+          rxrspflit = l2.module.io.lcreditCHI.get.rx.rsp.flit, rxrspflitv = l2.module.io.lcreditCHI.get.rx.rsp.flitv,
+          rxdatflit = l2.module.io.lcreditCHI.get.rx.dat.flit, rxdatflitv = l2.module.io.lcreditCHI.get.rx.dat.flitv,
+          rxsnpflit = l2.module.io.lcreditCHI.get.rx.snp.flit, rxsnpflitv = l2.module.io.lcreditCHI.get.rx.snp.flitv,
+          txrspflit = l2.module.io.lcreditCHI.get.tx.rsp.flit, txrspflitv = l2.module.io.lcreditCHI.get.tx.rsp.flitv,
+          txdatflit = l2.module.io.lcreditCHI.get.tx.dat.flit, txdatflitv = l2.module.io.lcreditCHI.get.tx.dat.flitv,
           time = time_sim, timev = extTime.B
         )
       }
 
-      l2.module.io.chi <> l3.io.rn(i)
+      l2.module.io.lcreditCHI.get <> l3.io.rn(i)
       dontTouch(l2.module.io)
 
       l2.module.io.l2_hint <> io_l1(i).l2Hint
@@ -342,8 +342,8 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1, issue:
   }
 }
 
-object TestTopSoCHelper {
-  def gen(fTop: Parameters => TestTopSoC)(args: Array[String]) = {
+object TestTopOpenLLCHelper {
+  def gen(fTop: Parameters => TestTopOpenLLC)(args: Array[String]) = {
     val FPGAPlatform    = false
     val enableChiselDB  = !FPGAPlatform && true
     val enableCHILog    = !FPGAPlatform && true
@@ -398,16 +398,16 @@ object TestTopSoCHelper {
   }
 }
 
-object TestTopSoC_SingleCore extends App {
-  TestTopSoCHelper.gen(p => new TestTopSoC(
+object TestTopOpenLLC_SingleCore extends App {
+  TestTopOpenLLCHelper.gen(p => new TestTopOpenLLC(
     numCores = 1,
     numULAgents = 2,
     banks = 1
   )(p))(args)
 }
 
-object TestTopSoC_DualCore extends App {
-  TestTopSoCHelper.gen(p => new TestTopSoC(
+object TestTopOpenLLC_DualCore extends App {
+  TestTopOpenLLCHelper.gen(p => new TestTopOpenLLC(
     numCores = 2,
     numULAgents = 2,
     banks = 1