[26.04_linux-nvidia-bos] MPAM update

Documentation/arch/arm64/mpam.rst

@@ -65,6 +65,28 @@ The supported features are:
   there is at least one CSU monitor on each MSC that makes up the L3 group.
   Exposing CSU counters from other caches or devices is not supported.
 
+* Memory Bandwidth Usage (MBWU) on or after the L3 cache.  resctrl uses the
+  L3 cache-id to identify where the memory bandwidth is measured. For this
+  reason the platform must have an L3 cache with cache-id's supplied by
+  firmware. (The platform doesn't need to support MPAM.)
+
+  Memory bandwidth monitoring makes use of MBWU monitors in each MSC that
+  makes up the L3 group. If the memory bandwidth monitoring is on the memory
+  rather than the L3 then there must be a single global L3 as otherwise it
+  is unknown which L3 the traffic came from.
+
+  To expose 'mbm_total_bytes', the topology of the group of MSC chosen must
+  match the topology of the L3 cache so that the cache-id's can be
+  repainted. For example: Platforms with Memory bandwidth monitors on
+  CPU-less NUMA nodes cannot expose 'mbm_total_bytes' as these nodes do not
+  have a corresponding L3 cache. 'mbm_local_bytes' is not exposed as MPAM
+  cannot distinguish local traffic from global traffic.
+
+  All these restrictions based on L3 cache are due to resctrl, currently, only
+  supporting monitoring at the L3 scope. It is expected that going forward more
+  MBWU monitors can be exposed to the user after support for more monitoring
+  scopes is added to resctrl.
+
 Reporting Bugs
 ==============
 If you are not seeing the counters or controls you expect please share the

Documentation/filesystems/resctrl.rst

@@ -439,9 +439,9 @@ with the following files:
 
 	Two MBM events are supported by default: mbm_local_bytes and mbm_total_bytes.
 	Each MBM event's sub-directory contains a file named "event_filter" that is
-	used to view and modify which memory transactions the MBM event is configured
-	with. The file is accessible only when "mbm_event" counter assignment mode is
-	enabled.
+	used to view and (if writable) modify which memory transactions the MBM event
+	is configured with. The file is accessible only when "mbm_event" counter
+	assignment mode is enabled.
 
 	List of memory transaction types supported:
 
@@ -466,9 +466,8 @@ with the following files:
 	  # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter
 	  local_reads,local_non_temporal_writes,local_reads_slow_memory
 
-	Modify the event configuration by writing to the "event_filter" file within
-	the "event_configs" directory. The read/write "event_filter" file contains the
-	configuration of the event that reflects which memory transactions are counted by it.
+	The memory transactions the MBM event is configured with can be changed
+	if "event_filter" is writable.
 
 	For example::
 
@@ -492,6 +491,12 @@ with the following files:
 	"1":
 		Auto assignment is enabled.
 
+	Automatic counter assignment is done with best effort. If auto
+	assignment is enabled but there are not enough available counters then
+	monitor group creation could succeed while one or more events belonging
+	to the group may not have a counter assigned in all domains. Consult
+	mbm_L3_assignments for counter assignment states of the new groups.
+
 	Example::
 
 	  # echo 0 > /sys/fs/resctrl/info/L3_MON/mbm_assign_on_mkdir
@@ -582,6 +587,11 @@ All groups contain the following files:
 	then the task must already belong to the CTRL_MON parent of this
 	group. The task is removed from any previous MON group.
 
+	When writing to this file, a task id of 0 is interpreted as the
+	task id of the currently running task. On reading the file, a task
+	id of 0 will never be shown and there is no representation of the
+	idle tasks. Instead, a CPU's idle task is always considered as a
+	member of the group owning the CPU.
 
 "cpus":
 	Reading this file shows a bitmask of the logical CPUs owned by

arch/arm64/kvm/hyp/vhe/sysreg-sr.c

@@ -183,6 +183,21 @@ void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt)
 }
 NOKPROBE_SYMBOL(sysreg_restore_guest_state_vhe);
 
+/*
+ * The _EL0 value was written by the host's context switch and belongs to the
+ * VMM. Copy this into the guest's _EL1 register.
+ */
+static inline void __mpam_guest_load(void)
+{
+	u64 mask = MPAM0_EL1_PARTID_D | MPAM0_EL1_PARTID_I | MPAM0_EL1_PMG_D | MPAM0_EL1_PMG_I;
+
+	if (system_supports_mpam()) {
+		u64 val = (read_sysreg_s(SYS_MPAM0_EL1) & mask) | MPAM1_EL1_MPAMEN;
+
+		write_sysreg_el1(val, SYS_MPAM1);
+	}
+}
+
 /**
  * __vcpu_load_switch_sysregs - Load guest system registers to the physical CPU
  *
@@ -222,6 +237,7 @@ void __vcpu_load_switch_sysregs(struct kvm_vcpu *vcpu)
 	 */
 	__sysreg32_restore_state(vcpu);
 	__sysreg_restore_user_state(guest_ctxt);
+	__mpam_guest_load();
 
 	if (unlikely(is_hyp_ctxt(vcpu))) {
 		__sysreg_restore_vel2_state(vcpu);

arch/x86/kernel/cpu/resctrl/monitor.c

@@ -464,6 +464,7 @@ int __init rdt_get_l3_mon_config(struct rdt_resource *r)
 	    (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL) ||
 	     rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL))) {
 		r->mon.mbm_cntr_assignable = true;
+		r->mon.mbm_cntr_configurable = true;
 		cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx);
 		r->mon.num_mbm_cntrs = (ebx & GENMASK(15, 0)) + 1;
 		hw_res->mbm_cntr_assign_enabled = true;

drivers/acpi/arm64/mpam.c

@@ -95,51 +95,17 @@ static void acpi_mpam_parse_irqs(struct platform_device *pdev,
 		res[(*res_idx)++] = DEFINE_RES_IRQ_NAMED(irq, "error");
 }
 
-#define UUID_MPAM_INTERCONNECT_TABLE		"fe2bd645-033b-49e6-9479-2e0b8b21d1cd"
-
-struct acpi_mpam_interconnect_descriptor_table {
-	u8	type_uuid[16];
-	u32	num_descriptors;
-};
-
-struct acpi_mpam_interconnect_descriptor {
-	u32	source_id;
-	u32	destination_id;
-	u8	link_type;
-	u8	reserved[3];
-};
-
-static int acpi_mpam_parse_resource(struct acpi_mpam_msc_node *tbl_msc,
-				    struct mpam_msc *msc,
+static int acpi_mpam_parse_resource(struct mpam_msc *msc,
 				    struct acpi_mpam_resource_node *res)
 {
-	struct acpi_mpam_interconnect_descriptor_table *tbl_int_tbl;
-	struct acpi_mpam_interconnect_descriptor *tbl_int;
-	guid_t int_tbl_uuid, spec_uuid;
 	int level, nid;
 	u32 cache_id;
-	off_t offset;
 
-	/*
-	 * Class IDs are somewhat arbitrary, but need to be co-ordinated.
-	 * 0-N are caches,
-	 * 64, 65: Interconnect, but ideally these would appear between the
-	 *     classes the controls are adjacent to.
-	 * 128: SMMU,
-	 * 192-192+level: Memory Side Caches, nothing checks that N is a
-	 *                small number.
-	 * 255: Memory Controllers
-	 *
-	 * ACPI devices would need a class id allocated based on the _HID.
-	 *
-	 * Classes that the mpam driver can't currently plumb into resctrl
-	 * are registered as UNKNOWN.
-	 */
 	switch (res->locator_type) {
 	case ACPI_MPAM_LOCATION_TYPE_PROCESSOR_CACHE:
 		cache_id = res->locator.cache_locator.cache_reference;
 		level = find_acpi_cache_level_from_id(cache_id);
-		if (level <= 0 || level >= 64) {
+		if (level <= 0) {
 			pr_err_once("Bad level (%d) for cache with id %u\n", level, cache_id);
 			return -EINVAL;
 		}
@@ -154,57 +120,6 @@ static int acpi_mpam_parse_resource(struct acpi_mpam_msc_node *tbl_msc,
 		}
 		return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_MEMORY,
 				       MPAM_CLASS_ID_DEFAULT, nid);
-	case ACPI_MPAM_LOCATION_TYPE_SMMU:
-		return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_UNKNOWN,
-				       128, res->locator.smmu_locator.smmu_interface);
-	case ACPI_MPAM_LOCATION_TYPE_MEMORY_CACHE:
-		cache_id = res->locator.mem_cache_locator.reference;
-		level = res->locator.mem_cache_locator.level;
-		if (192 + level >= 255) {
-			pr_err_once("Bad level (%u) for memory side cache with reference %u\n",
-				    level, cache_id);
-			return -EINVAL;
-		}
-
-		return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_CACHE,
-				       192 + level, cache_id);
-
-	case ACPI_MPAM_LOCATION_TYPE_INTERCONNECT:
-		/* Find the descriptor table, and check it lands in the parent msc */
-		offset = res->locator.interconnect_ifc_locator.inter_connect_desc_tbl_off;
-		if (offset >= tbl_msc->length) {
-			pr_err_once("Bad offset (%lu) for interconnect descriptor on msc %u\n",
-				    offset, tbl_msc->identifier);
-			return -EINVAL;
-		}
-		tbl_int_tbl = ACPI_ADD_PTR(struct acpi_mpam_interconnect_descriptor_table,
-					   tbl_msc, offset);
-		guid_parse(UUID_MPAM_INTERCONNECT_TABLE, &spec_uuid);
-		import_guid(&int_tbl_uuid, tbl_int_tbl->type_uuid);
-		if (!guid_equal(&spec_uuid, &int_tbl_uuid)) {
-			pr_err_once("Bad UUID for interconnect descriptor on msc %u\n",
-				    tbl_msc->identifier);
-			return -EINVAL;
-		}
-
-		offset += sizeof(*tbl_int_tbl);
-		offset += tbl_int_tbl->num_descriptors * sizeof(*tbl_int);
-		if (offset >= tbl_msc->length) {
-			pr_err_once("Bad num_descriptors (%u) for interconnect descriptor on msc %u\n",
-				    tbl_int_tbl->num_descriptors, tbl_msc->identifier);
-			return -EINVAL;
-		}
-
-		tbl_int = ACPI_ADD_PTR(struct acpi_mpam_interconnect_descriptor,
-				       tbl_int_tbl, sizeof(*tbl_int_tbl));
-		cache_id = tbl_int->source_id;
-
-		/* Unknown link type? */
-		if (tbl_int->link_type != 0 && tbl_int->link_type == 1)
-			return 0;
-
-		return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_UNKNOWN,
-				       64 + tbl_int->link_type, cache_id);
 	default:
 		/* These get discovered later and are treated as unknown */
 		return 0;
@@ -235,7 +150,7 @@ int acpi_mpam_parse_resources(struct mpam_msc *msc,
 			return -EINVAL;
 		}
 
-		err = acpi_mpam_parse_resource(tbl_msc, msc, resource);
+		err = acpi_mpam_parse_resource(msc, resource);
 		if (err)
 			return err;
 

drivers/iommu/iommu.c

@@ -2184,12 +2184,6 @@ void iommu_domain_free(struct iommu_domain *domain)
 }
 EXPORT_SYMBOL_GPL(iommu_domain_free);
 
-struct iommu_domain *iommu_get_domain_for_group(struct iommu_group *group)
-{
-	return group->domain;
-}
-EXPORT_SYMBOL_GPL(iommu_get_domain_for_group);
-
 /*
  * Put the group's domain back to the appropriate core-owned domain - either the
  * standard kernel-mode DMA configuration or an all-DMA-blocked domain.
@@ -2365,6 +2359,12 @@ struct iommu_domain *iommu_driver_get_domain_for_dev(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(iommu_driver_get_domain_for_dev);
 
+struct iommu_domain *iommu_get_domain_for_group(struct iommu_group *group)
+{
+	return group->domain;
+}
+EXPORT_SYMBOL_GPL(iommu_get_domain_for_group);
+
 /*
  * For IOMMU_DOMAIN_DMA implementations which already provide their own
  * guarantees that the group and its default domain are valid and correct.

drivers/pci/hotplug/pnv_php.c

@@ -813,7 +813,7 @@ static struct pnv_php_slot *pnv_php_alloc_slot(struct device_node *dn)
 	if (dn->child && PCI_DN(dn->child))
 		php_slot->slot_no = PCI_SLOT(PCI_DN(dn->child)->devfn);
 	else
-		php_slot->slot_no = -1;   /* Placeholder slot */
+		php_slot->slot_no = PCI_SLOT_PLACEHOLDER;   /* Placeholder slot */
 
 	kref_init(&php_slot->kref);
 	php_slot->state	                = PNV_PHP_STATE_INITIALIZED;

drivers/pci/hotplug/rpaphp_slot.c

@@ -85,7 +85,7 @@ int rpaphp_register_slot(struct slot *slot)
 	struct device_node *child;
 	u32 my_index;
 	int retval;
-	int slotno = -1;
+	int slotno = PCI_SLOT_PLACEHOLDER;
 
 	dbg("%s registering slot:path[%pOF] index[%x], name[%s] pdomain[%x] type[%d]\n",
 		__func__, slot->dn, slot->index, slot->name,

drivers/pci/msi/msi.c

@@ -873,6 +873,12 @@ void __pci_restore_msix_state(struct pci_dev *dev)
 	pci_intx_for_msi(dev, 0);
 	pci_msix_clear_and_set_ctrl(dev, 0,
 				PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
+
+	/*
+	 * The restored device state may not have Memory Space enabled.
+	 * Since the MSI-X Table and PBA are in Memory Space, enable it
+	 * while restoring them.
+	 */
 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
 	pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
 

drivers/pci/pci.c

@@ -723,6 +723,28 @@ u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)
 }
 EXPORT_SYMBOL_GPL(pci_find_dvsec_capability);
 
+static bool pci_dev_config_accessible(struct pci_dev *dev, char *msg)
+{
+	u32 val;
+
+	/*
+	 * If a device's config space is inaccessible, reads typically
+	 * return ~0.  Since Device and Vendor ID are always ~0 for VFs,
+	 * check the Command and Status registers instead.
+	 *
+	 * N.B. This is racy because the device may become inaccessible
+	 * before the next access.
+	 */
+	pci_read_config_dword(dev, PCI_COMMAND, &val);
+	if (PCI_POSSIBLE_ERROR(val)) {
+		pci_warn(dev, "Device config space inaccessible; unable to %s\n",
+				msg);
+		return false;
+	}
+
+	return true;
+}
+
 /**
  * pci_find_parent_resource - return resource region of parent bus of given
  *			      region
@@ -4333,6 +4355,9 @@ int pcie_flr(struct pci_dev *dev)
 {
 	int ret;
 
+	if (!pci_dev_config_accessible(dev, "FLR"))
+		return -ENOTTY;
+
 	if (!pci_wait_for_pending_transaction(dev))
 		pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
 
@@ -4867,8 +4892,9 @@ static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
 
 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
 {
-	if (dev->multifunction || dev->subordinate || !dev->slot ||
-	    dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
+	if (dev->subordinate || !dev->slot ||
+	    dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
+	    (dev->multifunction && !dev->slot->per_func_slot))
 		return -ENOTTY;
 
 	return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
@@ -5031,6 +5057,9 @@ static void pci_dev_save_and_disable(struct pci_dev *dev)
 	 */
 	pci_set_power_state(dev, PCI_D0);
 
+	if (!pci_dev_config_accessible(dev, "save state"))
+		return;
+
 	pci_save_state(dev);
 	/*
 	 * Disable the device by clearing the Command register, except for