Optimize offload weight pinning with mmap host registration#1206
Optimize offload weight pinning with mmap host registration#1206Fatemanx wants to merge 2 commits into
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Code Review
This pull request introduces an optimization to register existing CPU tensor storage as CUDA pinned host memory in-place using cudaHostRegister, avoiding unnecessary memory allocations and copies. It refactors embedding, matrix multiplication, normalization, and tensor classes to utilize the new create_pin_tensor and move_tensor_back_to_cpu utility functions, and adds a comprehensive test suite. Feedback was provided to make the unregister finalizer in lightx2v/common/ops/utils.py more robust during interpreter shutdown by capturing torch functions as default arguments to avoid potential AttributeError or NameError exceptions.
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Summary
This PR optimizes CPU offload weight loading by registering eligible CPU
tensor storage as CUDA pinned host memory in place.
For lazy-loaded safetensors weights, the previous path allocated a pinned CPU
tensor and copied the source CPU tensor into it. This change allows the
original CPU storage to be used directly as the pinned H2D source when no
dtype conversion is required, avoiding one extra host-side copy.
Changes
handling.
cudaHostRegisterfor eligible CPU tensors.registration is unavailable or dtype conversion is required.
to_cpu()does not write device data back into file-backed storage.
the shared helper.
scale/bias cases.
conversion, lazy reload, and CPU offload copy-back behavior.
Validation
CUDA_VISIBLE_DEVICES=1 PYTHONPATH=. python -m unittest
test_cases.test_mmap_pinned_weights
Ran 11 tests OK
Notes
The in-place registered CPU source is treated as readonly because offloaded
inference weights are immutable. Copy-based pinned buffers keep the previous
writable copy-back behavior.