Fix: comma-separated port declarations only process first port

[vjdeshmukh]

Bug

When a Verilog module declares multiple ports on a single line (e.g. input A, B;), the tool only classifies the first port and silently ignores the rest. This causes a misleading crash: "Some ports are not properly declared as an input or output" — even though the Verilog is perfectly valid.

Cause

In Module.swift, the code assumed each Decl node contains only one port declaration, always taking list[0] and ignoring any remaining items in the list.

Fix

Replace list[0] with a loop over all items in the list, so every port in a comma-separated declaration gets processed.

Impact

This bug causes fault to crash on any standard Verilog file that uses comma-separated port declarations (e.g. input A, B;), which is common in real-world netlists. This includes the ISCAS-89 benchmark suite where all 39 files use this style, making the entire sequential circuit benchmark suite unusable.