Validate store-before-load / writeback ordering at the LLC↔DRAM boundary on real HW

[tinebp]

Tracking issue split out from #340 (credit: @hwirys, found on real U250 hardware).

Concern

AXI4 does not order AW/AR transactions issued with different IDs (spec A5). In principle a load can bypass an in-flight store to the same line at the memory boundary, returning stale data.

Why not fix it in VX_axi_adapter

#340 proposed a global gate that stalls all reads while any write is outstanding. That serializes the entire memory pipeline and kills bandwidth — not how a GPU memory controller behaves — and it papers over an ordering guarantee that belongs upstream. VX_axi_adapter is a generic protocol-converter shared by every platform and both simulators; ordering policy should not live there.

Correct layer

In a write-back cache, same-line RAW never reaches DRAM (the dirty line stays in cache). The cases where ordering genuinely breaks at the LLC↔DRAM boundary are atomics and dirty-line writeback vs refill collisions — i.e. the LLC AMO/writeback ordering path (see ongoing fix_llc_amo_gating work).

Action

• Confirm whether Vortex's LLC can issue a refill and a writeback for the same line concurrently to the AXI master without ordering.
• Confirm AMO ordering at the LLC↔DRAM boundary is enforced (tie-in with the LLC AMO gating work).
• Validate store-before-load to the same address on real FPGA hardware (the symptom @hwirys originally observed on U250).

Note: the multi-bank addressing half of #340 is already resolved on master via #342 (U250 single-bank).