From b5ed1f89a1fd6d934d60f83ec31b71c942c3de79 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 21 Jun 2023 16:31:35 +0200 Subject: [PATCH 01/10] Fix xpulpbitop opcode definitions p.ror had only one source register but according to the docs it has two --- opcodes-xpulpbitop_CUSTOM | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/opcodes-xpulpbitop_CUSTOM b/opcodes-xpulpbitop_CUSTOM index eafe2209..4f227dc2 100644 --- a/opcodes-xpulpbitop_CUSTOM +++ b/opcodes-xpulpbitop_CUSTOM @@ -31,8 +31,8 @@ p.bsetr rd rs1 rs2 31..30=2 29..25=0 14..12=4 6..2=0x0C 1..0=3 p.bclr rd rs1 Luimm5 imm5 31..30=3 14..12=3 6..2=0x0C 1..0=3 p.bclrr rd rs1 rs2 31..30=2 29..25=0 14..12=3 6..2=0x0C 1..0=3 -p.cnt rd rs1 rs2 31..25=8 14..12=3 6..2=0x0C 1..0=3 -p.clb rd rs1 31..25=8 24..20=0 14..12=2 6..2=0x0C 1..0=3 -p.fl1 rd rs1 31..25=8 24..20=0 14..12=1 6..2=0x0C 1..0=3 +p.ror rd rs1 rs2 31..25=4 14..12=5 6..2=0x0C 1..0=3 p.ff1 rd rs1 31..25=8 24..20=0 14..12=0 6..2=0x0C 1..0=3 -p.ror rd rs1 31..25=4 24..20=0 14..12=5 6..2=0x0C 1..0=3 +p.fl1 rd rs1 31..25=8 24..20=0 14..12=1 6..2=0x0C 1..0=3 +p.clb rd rs1 31..25=8 24..20=0 14..12=2 6..2=0x0C 1..0=3 +p.cnt rd rs1 31..25=8 24..20=0 14..12=3 6..2=0x0C 1..0=3 From 1ef83f8175211867eadc242bab4d675fe05c1d74 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 21 Jun 2023 16:31:35 +0200 Subject: [PATCH 02/10] Add xpulpmacrnhi opcodes --- config.mk | 1 + opcodes-xpulpmacrnhi_CUSTOM | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 opcodes-xpulpmacrnhi_CUSTOM diff --git a/config.mk b/config.mk index bb86b771..db63f013 100644 --- a/config.mk +++ b/config.mk @@ -4,6 +4,7 @@ # Xpulpimg RV32XPULPIMG := opcodes-xpulpabs_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip_CUSTOM opcodes-xpulpmacsi_CUSTOM opcodes-xpulpminmax_CUSTOM opcodes-xpulpslet_CUSTOM opcodes-xpulpvect_CUSTOM opcodes-xpulpvectshufflepack_CUSTOM +RV32XPULPIMG += opcodes-xpulpmacrnhi_CUSTOM RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM # RV32XPULPIMG += opcodes-xpulpbitopsmall_CUSTOM #is a subset of opcodes-xpulpbitop_CUSTOM # RV32XPULPIMG += opcodes-xpulppostmod_CUSTOM #conflict with opcodes-ssr_CUSTOM diff --git a/opcodes-xpulpmacrnhi_CUSTOM b/opcodes-xpulpmacrnhi_CUSTOM new file mode 100644 index 00000000..497865aa --- /dev/null +++ b/opcodes-xpulpmacrnhi_CUSTOM @@ -0,0 +1,23 @@ +# Xpulp extension subset: 16x16->32bit MAC with round and norm operations + +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm, +# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo, +# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2, +# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5, +# vseglen, stagger_max, stagger_mask + +# rs3 is rd hence it does not appear here +p.macuN rd rs1 rs2 Luimm5 31..30=0 14..12=1 6..2=0x16 1..0=3 +p.machhuN rd rs1 rs2 Luimm5 31..30=1 14..12=1 6..2=0x16 1..0=3 +p.macsN rd rs1 rs2 Luimm5 31..30=2 14..12=1 6..2=0x16 1..0=3 +p.machhsN rd rs1 rs2 Luimm5 31..30=3 14..12=1 6..2=0x16 1..0=3 +p.macsRN rd rs1 rs2 Luimm5 31..30=2 14..12=5 6..2=0x16 1..0=3 +p.machhsRN rd rs1 rs2 Luimm5 31..30=3 14..12=5 6..2=0x16 1..0=3 +p.macuRN rd rs1 rs2 Luimm5 31..30=0 14..12=5 6..2=0x16 1..0=3 +p.machhuRN rd rs1 rs2 Luimm5 31..30=1 14..12=5 6..2=0x16 1..0=3 From 388fd70030dfeb89ba413e3c7d9e8537c55cb3bc Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 21 Jun 2023 16:31:35 +0200 Subject: [PATCH 03/10] Add HW Loop Control and Status Registers Different implementations have edited the encoding file directly instead of generating it, this has caused diverging definitions of the addresses used. The current default are the PULPv3 addresses that completely avoid any known conflicts. Other options are included but commented-out for the sake of documentation and completeness. --- parse_opcodes | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/parse_opcodes b/parse_opcodes index 817ae4fe..c2aa26d8 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -123,8 +123,35 @@ csrs = [ (0x043, 'utval'), (0x044, 'uip'), - # Custom User R/W + # Custom User R/W Snitch (0x800, 'fmode'), + + # Custom User R/W Xpulp + # HW Loop Registers for PULPv3 + (0x7C0, 'lpstart0'), + (0x7C1, 'lpend0'), + (0x7C2, 'lpcount0'), + (0x7C4, 'lpstart1'), + (0x7C5, 'lpsend1'), + (0x7C6, 'lpcount1'), + + # HW Loop as defined by CV32E40P + # Snitch added fmode at 0x800 breaking compatibility + # (0x800, 'lpstart0'), + # (0x801, 'lpend0'), + # (0x802, 'lpcount0'), + # (0x804, 'lpstart1'), + # (0x805, 'lpsend1'), + # (0x806, 'lpcount1'), + + # HW Loop for PULPv1, DO NOT USE + # collides with debug mode regs (dcsr, dpc, dscratch) + # (0x7B0, 'lpstart0'), + # (0x7B1, 'lpend0'), + # (0x7B2, 'lpcount0'), + # (0x7B4, 'lpstart1'), + # (0x7B5, 'lpsend1'), + # (0x7B6, 'lpcount1'), # Standard User RO (0xC00, 'cycle'), From d2cf13f423b6bc30ba593250c07235f7458bc8e9 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 21 Jun 2023 16:31:35 +0200 Subject: [PATCH 04/10] Change default HW-Loop CSRs, document collisions --- README.md | 24 ++++++++++++++++++++++++ parse_opcodes | 37 ++++++++++++++++++++----------------- 2 files changed, 44 insertions(+), 17 deletions(-) diff --git a/README.md b/README.md index 0e2d63cc..9877296f 100644 --- a/README.md +++ b/README.md @@ -47,3 +47,27 @@ Ariane and Snitch do not use the same FPU configuration. There might be some overlap in opcodes between extensions. These are noted as far as known in the corresponding files. In some cases these overlaps can be avoided by making one of the opcodes a pseudo-opcodes using `@` in front. + +## Control and Status Registers + +### HW-Loop Register Collisions + +There are three existing address spaces for the HW-Loop [CSRs defined in binutils](https://iis-git.ee.ethz.ch/gnu/riscv-binutils-gdb/-/blob/riscv-binutils-2.34-pulp/include/opcode/riscv-opc.h#L829), all of them have collisions. +The default configuration uses the CV32E40P addresses. + +#### CV32E40P + +The addresses 0x800-0x802 and 0x804-0x806 are used, this collides with the fmode CSR used in Snitch. +The source of the HW-Loop addresses: https://cv32e40p.readthedocs.io/en/latest/control_status_registers/ +The [offending riscv-opcodes commit](https://github.com/pulp-platform/riscv-opcodes/commit/1e5fa7787b4e388c51956f6e7fd26d4d249a7d80) that adds the collisions from Snitch: (file parse_opcodes, line 124) + +#### PULPv3 + +The addresses 0x7C0 - 0x7C2 and 0x7C4-0x7C6 are used, this collides with the ssr and fpmode CSRs used in Snitch. +The [offending riscv-opcodes commit](https://github.com/pulp-platform/riscv-opcodes/commit/1e5fa7787b4e388c51956f6e7fd26d4d249a7d80) that adds the collisions from Snitch: (file parse_opcodes, line 133-134) + +#### PULPv1 + +The addresses 0x7B0 - 0x7B2 and 0x7B4-0x7B6 are used, this collides with the debug mode registers (dcsr, dpc, dscratch0) from the official spec (page 11 in [RISCV priviliged v1.12](https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf)). +There is no reason to use this for anything new, it is considered DEPRECATED. + diff --git a/parse_opcodes b/parse_opcodes index c2aa26d8..a8b9e08b 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -124,28 +124,31 @@ csrs = [ (0x044, 'uip'), # Custom User R/W Snitch - (0x800, 'fmode'), + # Removed due to collisions with HW Loop + # Todo: Find a better solution + # (0x800, 'fmode'), # Custom User R/W Xpulp - # HW Loop Registers for PULPv3 - (0x7C0, 'lpstart0'), - (0x7C1, 'lpend0'), - (0x7C2, 'lpcount0'), - (0x7C4, 'lpstart1'), - (0x7C5, 'lpsend1'), - (0x7C6, 'lpcount1'), - # HW Loop as defined by CV32E40P - # Snitch added fmode at 0x800 breaking compatibility - # (0x800, 'lpstart0'), - # (0x801, 'lpend0'), - # (0x802, 'lpcount0'), - # (0x804, 'lpstart1'), - # (0x805, 'lpsend1'), - # (0x806, 'lpcount1'), + # Collides with Snitch CSRs, namely fmode at 0x800 + (0x800, 'lpstart0'), + (0x801, 'lpend0'), + (0x802, 'lpcount0'), + (0x804, 'lpstart1'), + (0x805, 'lpsend1'), + (0x806, 'lpcount1'), + + # HW Loop Registers for PULPv3 + # Collides with Snitch CSRs, namely ssr and fpmode at 0x7C0-0x7C1 + # (0x7C0, 'lpstart0'), + # (0x7C1, 'lpend0'), + # (0x7C2, 'lpcount0'), + # (0x7C4, 'lpstart1'), + # (0x7C5, 'lpsend1'), + # (0x7C6, 'lpcount1'), # HW Loop for PULPv1, DO NOT USE - # collides with debug mode regs (dcsr, dpc, dscratch) + # Collides with debug mode regs (dcsr, dpc, dscratch) # (0x7B0, 'lpstart0'), # (0x7B1, 'lpend0'), # (0x7B2, 'lpcount0'), From e9cbc880d5f58c65ee62a272bef7a77df5be338d Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 21 Jun 2023 16:31:35 +0200 Subject: [PATCH 05/10] Add hwloop to make, fix csr names --- config.mk | 1 + opcodes-xpulphwloop_CUSTOM | 6 +++--- parse_opcodes | 6 +++--- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/config.mk b/config.mk index db63f013..d87ca538 100644 --- a/config.mk +++ b/config.mk @@ -6,6 +6,7 @@ RV32XPULPIMG := opcodes-xpulpabs_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip_CUSTOM opcodes-xpulpmacsi_CUSTOM opcodes-xpulpminmax_CUSTOM opcodes-xpulpslet_CUSTOM opcodes-xpulpvect_CUSTOM opcodes-xpulpvectshufflepack_CUSTOM RV32XPULPIMG += opcodes-xpulpmacrnhi_CUSTOM RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM +RV32XPULPIMG += opcodes-xpulphwloop_CUSTOM # RV32XPULPIMG += opcodes-xpulpbitopsmall_CUSTOM #is a subset of opcodes-xpulpbitop_CUSTOM # RV32XPULPIMG += opcodes-xpulppostmod_CUSTOM #conflict with opcodes-ssr_CUSTOM diff --git a/opcodes-xpulphwloop_CUSTOM b/opcodes-xpulphwloop_CUSTOM index 362992cf..b09709ed 100644 --- a/opcodes-xpulphwloop_CUSTOM +++ b/opcodes-xpulphwloop_CUSTOM @@ -16,7 +16,7 @@ lp.starti L imm12 19..15=0 14..12=0 11..8=0 6..2=0x1E 1..0=3 lp.endi L imm12 19..15=0 14..12=1 11..8=0 6..2=0x1E 1..0=3 -lp.count L rs1 31..20=0 14..12=2 11..8=0 6..2=0x1E 1..0=3 +lp.count L rs1 31..20=0 14..12=2 11..8=0 6..2=0x1E 1..0=3 lp.counti L imm12 19..15=0 14..12=3 11..8=0 6..2=0x1E 1..0=3 -lp.setup L rs1 imm12 14..12=4 11..8=0 6..2=0x1E 1..0=3 -lp.setupi L imm12 uimms 14..12=5 11..8=0 6..2=0x1E 1..0=3 +lp.setup L rs1 imm12 14..12=4 11..8=0 6..2=0x1E 1..0=3 +lp.setupi L imm12 uimms 14..12=5 11..8=0 6..2=0x1E 1..0=3 diff --git a/parse_opcodes b/parse_opcodes index a8b9e08b..0df508ee 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -135,7 +135,7 @@ csrs = [ (0x801, 'lpend0'), (0x802, 'lpcount0'), (0x804, 'lpstart1'), - (0x805, 'lpsend1'), + (0x805, 'lpend1'), (0x806, 'lpcount1'), # HW Loop Registers for PULPv3 @@ -144,7 +144,7 @@ csrs = [ # (0x7C1, 'lpend0'), # (0x7C2, 'lpcount0'), # (0x7C4, 'lpstart1'), - # (0x7C5, 'lpsend1'), + # (0x7C5, 'lpend1'), # (0x7C6, 'lpcount1'), # HW Loop for PULPv1, DO NOT USE @@ -153,7 +153,7 @@ csrs = [ # (0x7B1, 'lpend0'), # (0x7B2, 'lpcount0'), # (0x7B4, 'lpstart1'), - # (0x7B5, 'lpsend1'), + # (0x7B5, 'lpend1'), # (0x7B6, 'lpcount1'), # Standard User RO From 479df48859a9b63da9f479f38fc95c854851c9a7 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 21 Jun 2023 16:31:35 +0200 Subject: [PATCH 06/10] Add bitrev subset as custom extension --- config.mk | 1 + opcodes-xpulbitrev_CUSTOM | 15 +++++++++++++++ parse_opcodes | 1 + 3 files changed, 17 insertions(+) create mode 100644 opcodes-xpulbitrev_CUSTOM diff --git a/config.mk b/config.mk index d87ca538..14dd4e19 100644 --- a/config.mk +++ b/config.mk @@ -7,6 +7,7 @@ RV32XPULPIMG := opcodes-xpulpabs_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip RV32XPULPIMG += opcodes-xpulpmacrnhi_CUSTOM RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM RV32XPULPIMG += opcodes-xpulphwloop_CUSTOM +RV32XPULPIMG += opcodes-xpulbitrev_CUSTOM # RV32XPULPIMG += opcodes-xpulpbitopsmall_CUSTOM #is a subset of opcodes-xpulpbitop_CUSTOM # RV32XPULPIMG += opcodes-xpulppostmod_CUSTOM #conflict with opcodes-ssr_CUSTOM diff --git a/opcodes-xpulbitrev_CUSTOM b/opcodes-xpulbitrev_CUSTOM new file mode 100644 index 00000000..8013c967 --- /dev/null +++ b/opcodes-xpulbitrev_CUSTOM @@ -0,0 +1,15 @@ +# Xpulp extension subset: bit reverse operation + +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm, +# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo, +# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2, +# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5, Luimm2 +# vseglen, stagger_max, stagger_mask + +p.bitrev rd rs1 Luimm2 imm5 31..30=3 29..27=0 14..12=5 6..2=0x0C 1..0=3 diff --git a/parse_opcodes b/parse_opcodes index 0df508ee..c2c667a0 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -55,6 +55,7 @@ arglut['prs3'] = (11,7) arglut['L'] = (7,7) arglut['uimms'] = (19,15) arglut['Luimm5'] = (29,25) +arglut['Luimm2'] = (26,25) arglut['vseglen'] = (31,29) arglut['stagger_max'] = (14,12) arglut['stagger_mask'] = (11,8) From 904400b135968c6948a850c592bd882f203ab8a1 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 21 Jun 2023 16:31:35 +0200 Subject: [PATCH 07/10] Add mulrnhi opcodes --- config.mk | 1 + opcodes-xpulpmulrnhi_CUSTOM | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 opcodes-xpulpmulrnhi_CUSTOM diff --git a/config.mk b/config.mk index 14dd4e19..aa25e0c2 100644 --- a/config.mk +++ b/config.mk @@ -4,6 +4,7 @@ # Xpulpimg RV32XPULPIMG := opcodes-xpulpabs_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip_CUSTOM opcodes-xpulpmacsi_CUSTOM opcodes-xpulpminmax_CUSTOM opcodes-xpulpslet_CUSTOM opcodes-xpulpvect_CUSTOM opcodes-xpulpvectshufflepack_CUSTOM +RV32XPULPIMG += opcodes-xpulpmulrnhi_CUSTOM RV32XPULPIMG += opcodes-xpulpmacrnhi_CUSTOM RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM RV32XPULPIMG += opcodes-xpulphwloop_CUSTOM diff --git a/opcodes-xpulpmulrnhi_CUSTOM b/opcodes-xpulpmulrnhi_CUSTOM new file mode 100644 index 00000000..1b53f334 --- /dev/null +++ b/opcodes-xpulpmulrnhi_CUSTOM @@ -0,0 +1,22 @@ +# Xpulp extension subset: 16x16->32bit MUL with round and norm operations + +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm, +# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo, +# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2, +# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5, +# vseglen, stagger_max, stagger_mask + +p.muluN rd rs1 rs2 Luimm5 31..30=0 14..12=0 6..2=0x16 1..0=3 +p.mulhhuN rd rs1 rs2 Luimm5 31..30=1 14..12=0 6..2=0x16 1..0=3 +p.mulsN rd rs1 rs2 Luimm5 31..30=2 14..12=0 6..2=0x16 1..0=3 +p.mulhhsN rd rs1 rs2 Luimm5 31..30=3 14..12=0 6..2=0x16 1..0=3 +p.muluRN rd rs1 rs2 Luimm5 31..30=0 14..12=4 6..2=0x16 1..0=3 +p.mulhhuRN rd rs1 rs2 Luimm5 31..30=1 14..12=4 6..2=0x16 1..0=3 +p.mulsRN rd rs1 rs2 Luimm5 31..30=2 14..12=4 6..2=0x16 1..0=3 +p.mulhhsRN rd rs1 rs2 Luimm5 31..30=3 14..12=4 6..2=0x16 1..0=3 From 87491b5e043d6a6379e6af82c426f4d3c103f9a8 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 21 Jun 2023 16:31:35 +0200 Subject: [PATCH 08/10] Add mulrnhi and partmac pseudo opcodes Technically partmac is not a pseudo and it should be possible to use it independently. --- config.mk | 1 + opcodes-xpulpmulrnhi_CUSTOM | 5 +++++ opcodes-xpulppartmac_CUSTOM | 19 +++++++++++++++++++ 3 files changed, 25 insertions(+) create mode 100644 opcodes-xpulppartmac_CUSTOM diff --git a/config.mk b/config.mk index aa25e0c2..2c7b6d63 100644 --- a/config.mk +++ b/config.mk @@ -5,6 +5,7 @@ # Xpulpimg RV32XPULPIMG := opcodes-xpulpabs_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip_CUSTOM opcodes-xpulpmacsi_CUSTOM opcodes-xpulpminmax_CUSTOM opcodes-xpulpslet_CUSTOM opcodes-xpulpvect_CUSTOM opcodes-xpulpvectshufflepack_CUSTOM RV32XPULPIMG += opcodes-xpulpmulrnhi_CUSTOM +RV32XPULPIMG += opcodes-xpulppartmac_CUSTOM # subset of xpulpmacrnhi (declared as pseudo instructions) RV32XPULPIMG += opcodes-xpulpmacrnhi_CUSTOM RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM RV32XPULPIMG += opcodes-xpulphwloop_CUSTOM diff --git a/opcodes-xpulpmulrnhi_CUSTOM b/opcodes-xpulpmulrnhi_CUSTOM index 1b53f334..eff9d014 100644 --- a/opcodes-xpulpmulrnhi_CUSTOM +++ b/opcodes-xpulpmulrnhi_CUSTOM @@ -20,3 +20,8 @@ p.muluRN rd rs1 rs2 Luimm5 31..30=0 14..12=4 6..2=0x16 1..0=3 p.mulhhuRN rd rs1 rs2 Luimm5 31..30=1 14..12=4 6..2=0x16 1..0=3 p.mulsRN rd rs1 rs2 Luimm5 31..30=2 14..12=4 6..2=0x16 1..0=3 p.mulhhsRN rd rs1 rs2 Luimm5 31..30=3 14..12=4 6..2=0x16 1..0=3 + +@p.mulu rd rs1 rs2 31..30=0 29..25=0 14..12=0 6..2=0x16 1..0=3 +@p.mulhhu rd rs1 rs2 31..30=1 29..25=0 14..12=0 6..2=0x16 1..0=3 +@p.muls rd rs1 rs2 31..30=2 29..25=0 14..12=0 6..2=0x16 1..0=3 +@p.mulhhs rd rs1 rs2 31..30=3 29..25=0 14..12=0 6..2=0x16 1..0=3 diff --git a/opcodes-xpulppartmac_CUSTOM b/opcodes-xpulppartmac_CUSTOM new file mode 100644 index 00000000..84438770 --- /dev/null +++ b/opcodes-xpulppartmac_CUSTOM @@ -0,0 +1,19 @@ +# Xpulp extension subset: 16x16->32bit MAC (pseudo of macrnhi) + +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm, +# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo, +# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2, +# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5, +# vseglen, stagger_max, stagger_mask + +# remove '@' if xpulpmacrnhi is not in use +@p.macu rd rs1 rs2 31..30=0 29..25=0 14..12=1 6..2=0x16 1..0=3 +@p.machhu rd rs1 rs2 31..30=1 29..25=0 14..12=1 6..2=0x16 1..0=3 +@p.macs rd rs1 rs2 31..30=2 29..25=0 14..12=1 6..2=0x16 1..0=3 +@p.machhs rd rs1 rs2 31..30=3 29..25=0 14..12=1 6..2=0x16 1..0=3 From fd8fec93eef76618ea3a04e14222f7c5abb36191 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 21 Jun 2023 16:31:35 +0200 Subject: [PATCH 09/10] Add addsubrn opcodes and p.avg(u) as pseudos --- config.mk | 1 + opcodes-xpulpaddsubrn_CUSTOM | 31 +++++++++++++++++++++++++++++++ opcodes-xpulpminmax_CUSTOM | 8 +++++--- 3 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 opcodes-xpulpaddsubrn_CUSTOM diff --git a/config.mk b/config.mk index 2c7b6d63..ff8b4d55 100644 --- a/config.mk +++ b/config.mk @@ -7,6 +7,7 @@ RV32XPULPIMG := opcodes-xpulpabs_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip RV32XPULPIMG += opcodes-xpulpmulrnhi_CUSTOM RV32XPULPIMG += opcodes-xpulppartmac_CUSTOM # subset of xpulpmacrnhi (declared as pseudo instructions) RV32XPULPIMG += opcodes-xpulpmacrnhi_CUSTOM +RV32XPULPIMG += opcodes-xpulpaddsubrn_CUSTOM RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM RV32XPULPIMG += opcodes-xpulphwloop_CUSTOM RV32XPULPIMG += opcodes-xpulbitrev_CUSTOM diff --git a/opcodes-xpulpaddsubrn_CUSTOM b/opcodes-xpulpaddsubrn_CUSTOM new file mode 100644 index 00000000..0292096b --- /dev/null +++ b/opcodes-xpulpaddsubrn_CUSTOM @@ -0,0 +1,31 @@ +# Xpulp extension subset: addition/subtraction with round and norm operations + +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm, +# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo, +# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2, +# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5, +# vseglen, stagger_max, stagger_mask + +p.addN rd rs1 rs2 Luimm5 31..30=0 14..12=2 6..2=0x16 1..0=3 +p.adduN rd rs1 rs2 Luimm5 31..30=2 14..12=2 6..2=0x16 1..0=3 +p.addRN rd rs1 rs2 Luimm5 31..30=0 14..12=6 6..2=0x16 1..0=3 +p.adduRN rd rs1 rs2 Luimm5 31..30=2 14..12=6 6..2=0x16 1..0=3 +p.subN rd rs1 rs2 Luimm5 31..30=0 14..12=3 6..2=0x16 1..0=3 +p.subuN rd rs1 rs2 Luimm5 31..30=2 14..12=3 6..2=0x16 1..0=3 +p.subRN rd rs1 rs2 Luimm5 31..30=0 14..12=7 6..2=0x16 1..0=3 +p.subuRN rd rs1 rs2 Luimm5 31..30=2 14..12=7 6..2=0x16 1..0=3 + +p.addNr rd rs1 rs2 31..30=1 29..25=0 14..12=2 6..2=0x16 1..0=3 +p.adduNr rd rs1 rs2 31..30=3 29..25=0 14..12=2 6..2=0x16 1..0=3 +p.addRNr rd rs1 rs2 31..30=1 29..25=0 14..12=6 6..2=0x16 1..0=3 +p.adduRNr rd rs1 rs2 31..30=3 29..25=0 14..12=6 6..2=0x16 1..0=3 +p.subNr rd rs1 rs2 31..30=1 29..25=0 14..12=3 6..2=0x16 1..0=3 +p.subuNr rd rs1 rs2 31..30=3 29..25=0 14..12=3 6..2=0x16 1..0=3 +p.subRNr rd rs1 rs2 31..30=1 29..25=0 14..12=7 6..2=0x16 1..0=3 +p.subuRNr rd rs1 rs2 31..30=3 29..25=0 14..12=7 6..2=0x16 1..0=3 diff --git a/opcodes-xpulpminmax_CUSTOM b/opcodes-xpulpminmax_CUSTOM index 964a2075..2789b39b 100644 --- a/opcodes-xpulpminmax_CUSTOM +++ b/opcodes-xpulpminmax_CUSTOM @@ -18,6 +18,8 @@ p.min rd rs1 rs2 31..25=2 14..12=4 6..2=0x0C 1..0=3 p.minu rd rs1 rs2 31..25=2 14..12=5 6..2=0x0C 1..0=3 p.max rd rs1 rs2 31..25=2 14..12=6 6..2=0x0C 1..0=3 p.maxu rd rs1 rs2 31..25=2 14..12=7 6..2=0x0C 1..0=3 -# might be missing p.avg, p.avgu respectively p.addN, p.adduN -p.addN rd rs1 rs2 31..30=0 Luimm5 14..12=2 6..2=0x16 1..0=3 -p.adduN rd rs1 rs2 31..30=2 Luimm5 14..12=2 6..2=0x16 1..0=3 + +# pulp >= v2: p.addN, p.adduN in addsubrn replaces p.avg, p.avgu +# -> pseudo op for compatibility +@p.avg rd rs1 rs2 31..30=0 Luimm5 14..12=2 6..2=0x16 1..0=3 +@p.avgu rd rs1 rs2 31..30=2 Luimm5 14..12=2 6..2=0x16 1..0=3 From f3631db2f11e62bde952c0935eec3c702f5057ed Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Wed, 21 Jun 2023 16:31:35 +0200 Subject: [PATCH 10/10] Add vectcomplex opcodes --- config.mk | 36 ++++++++++++++++++++++++++------- opcodes-xpulpvectcomplex_CUSTOM | 31 ++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 7 deletions(-) create mode 100644 opcodes-xpulpvectcomplex_CUSTOM diff --git a/config.mk b/config.mk index ff8b4d55..ff7d7ae5 100644 --- a/config.mk +++ b/config.mk @@ -2,18 +2,40 @@ # RV32IMA := opcodes-rv32i opcodes-rv32m opcodes-rv32a opcodes-system -# Xpulpimg -RV32XPULPIMG := opcodes-xpulpabs_CUSTOM opcodes-xpulpbr_CUSTOM opcodes-xpulpclip_CUSTOM opcodes-xpulpmacsi_CUSTOM opcodes-xpulpminmax_CUSTOM opcodes-xpulpslet_CUSTOM opcodes-xpulpvect_CUSTOM opcodes-xpulpvectshufflepack_CUSTOM -RV32XPULPIMG += opcodes-xpulpmulrnhi_CUSTOM -RV32XPULPIMG += opcodes-xpulppartmac_CUSTOM # subset of xpulpmacrnhi (declared as pseudo instructions) -RV32XPULPIMG += opcodes-xpulpmacrnhi_CUSTOM -RV32XPULPIMG += opcodes-xpulpaddsubrn_CUSTOM -RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM +# XPULPIMG +# Branching +RV32XPULPIMG := opcodes-xpulpbr_CUSTOM RV32XPULPIMG += opcodes-xpulphwloop_CUSTOM + +# Comparison +RV32XPULPIMG += opcodes-xpulpslet_CUSTOM + +# Bit Twiddle +RV32XPULPIMG += opcodes-xpulpbitop_CUSTOM RV32XPULPIMG += opcodes-xpulbitrev_CUSTOM # RV32XPULPIMG += opcodes-xpulpbitopsmall_CUSTOM #is a subset of opcodes-xpulpbitop_CUSTOM + +# Load/Store # RV32XPULPIMG += opcodes-xpulppostmod_CUSTOM #conflict with opcodes-ssr_CUSTOM +# Arithmetic +RV32XPULPIMG += opcodes-xpulpabs_CUSTOM +RV32XPULPIMG += opcodes-xpulpclip_CUSTOM +RV32XPULPIMG += opcodes-xpulpminmax_CUSTOM +RV32XPULPIMG += opcodes-xpulpmacsi_CUSTOM +RV32XPULPIMG += opcodes-xpulppartmac_CUSTOM # subset of xpulpmacrnhi (declared as pseudo instructions) + +# Arithmetic with round and norm +RV32XPULPIMG += opcodes-xpulpaddsubrn_CUSTOM +RV32XPULPIMG += opcodes-xpulpmulrnhi_CUSTOM +RV32XPULPIMG += opcodes-xpulpmacrnhi_CUSTOM + +# Packed SIMD +RV32XPULPIMG += opcodes-xpulpvect_CUSTOM +RV32XPULPIMG += opcodes-xpulpvectcomplex_CUSTOM +RV32XPULPIMG += opcodes-xpulpvectshufflepack_CUSTOM + + # Snitch SNITCH_OPCODES := opcodes-dma_CUSTOM opcodes-frep_CUSTOM opcodes-ssr_CUSTOM diff --git a/opcodes-xpulpvectcomplex_CUSTOM b/opcodes-xpulpvectcomplex_CUSTOM new file mode 100644 index 00000000..68fcb31c --- /dev/null +++ b/opcodes-xpulpvectcomplex_CUSTOM @@ -0,0 +1,31 @@ +# Xpulp extension subset: SIMD complex operations with format: (16bit imag, 16bit real) +# and SIMD comparison operations + +# format of a line in this file: +# +# +# is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# is one of rd, rs1, rs2, rs3, aqrl, fm, pred, succ, rm, +# funct3, imm20, jimm20, imm12, imm12hi, bimm12hi, imm12lo, +# bimm12lo, zimm, shamt, shamtw, imm5, imm6, vd, vs3, vs1, vs2, +# vm, wd, amoop, nf, simm5, zimm11, prs3, L, uimms, Luimm5, +# vseglen, stagger_max, stagger_mask + +pv.cplxconj.h rd rs1 31..27=0x0b 26=1 25=0 24..20=0 14..12=0 6..2=0x15 1..0=3 + +pv.subrotmj.h rd rs1 rs2 31..27=0x0d 26=1 25=0 14..12=0 6..2=0x15 1..0=3 +pv.subrotmj.h.div2 rd rs1 rs2 31..27=0x0d 26=1 25=0 14..12=2 6..2=0x15 1..0=3 +pv.subrotmj.h.div4 rd rs1 rs2 31..27=0x0d 26=1 25=0 14..12=4 6..2=0x15 1..0=3 +pv.subrotmj.h.div8 rd rs1 rs2 31..27=0x0d 26=1 25=0 14..12=6 6..2=0x15 1..0=3 + +pv.cplxmul.h.r rd rs1 rs2 31..27=0x0a 26=1 25=0 14..12=0 6..2=0x15 1..0=3 +pv.cplxmul.h.r.div2 rd rs1 rs2 31..27=0x0a 26=1 25=0 14..12=2 6..2=0x15 1..0=3 +pv.cplxmul.h.r.div4 rd rs1 rs2 31..27=0x0a 26=1 25=0 14..12=4 6..2=0x15 1..0=3 +pv.cplxmul.h.r.div8 rd rs1 rs2 31..27=0x0a 26=1 25=0 14..12=6 6..2=0x15 1..0=3 + +pv.cplxmul.h.i rd rs1 rs2 31..27=0x0a 26=1 25=1 14..12=0 6..2=0x15 1..0=3 +pv.cplxmul.h.i.div2 rd rs1 rs2 31..27=0x0a 26=1 25=1 14..12=2 6..2=0x15 1..0=3 +pv.cplxmul.h.i.div4 rd rs1 rs2 31..27=0x0a 26=1 25=1 14..12=4 6..2=0x15 1..0=3 +pv.cplxmul.h.i.div8 rd rs1 rs2 31..27=0x0a 26=1 25=1 14..12=6 6..2=0x15 1..0=3