From c23ed0578f62bb7aed135e732b2b3d8026264ac7 Mon Sep 17 00:00:00 2001 From: Kinza Qamar Date: Tue, 28 Apr 2026 17:40:23 +0100 Subject: [PATCH 1/2] [Clean-ups] Removed the unused peripheral clock interface Signed-off-by: Kinza Qamar --- hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv | 1 - hw/top_chip/dv/env/top_chip_dv_env.sv | 4 ---- hw/top_chip/dv/env/top_chip_dv_env_cfg.sv | 1 - hw/top_chip/dv/tb/tb.sv | 5 ----- 4 files changed, 11 deletions(-) diff --git a/hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv b/hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv index 7cf007973..2ba9607a4 100644 --- a/hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv +++ b/hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv @@ -92,7 +92,6 @@ task top_chip_dv_base_vseq::apply_reset(string kind = "HARD"); begin : isolation_fork fork cfg.sys_clk_vif.apply_reset(); - cfg.peri_clk_vif.apply_reset(); join_none wait fork; end : isolation_fork diff --git a/hw/top_chip/dv/env/top_chip_dv_env.sv b/hw/top_chip/dv/env/top_chip_dv_env.sv index 9440dd4e3..b8896f4d1 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env.sv +++ b/hw/top_chip/dv/env/top_chip_dv_env.sv @@ -67,10 +67,6 @@ function void top_chip_dv_env::build_phase(uvm_phase phase); `uvm_fatal(`gfn, "Cannot get sys_clk_vif") end - if (!uvm_config_db#(virtual clk_rst_if)::get(this, "", "peri_clk_if", cfg.peri_clk_vif)) begin - `uvm_fatal(`gfn, "Cannot get peri_clk_vif") - end - // Instantiate UART agent m_uart_agent = uart_agent::type_id::create("m_uart_agent", this); uvm_config_db#(uart_agent_cfg)::set(this, "m_uart_agent*", "cfg", cfg.m_uart_agent_cfg); diff --git a/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv b/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv index 9611f6fb7..c3aef365d 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv +++ b/hw/top_chip/dv/env/top_chip_dv_env_cfg.sv @@ -8,7 +8,6 @@ class top_chip_dv_env_cfg extends uvm_object; // External interfaces virtual clk_rst_if sys_clk_vif; - virtual clk_rst_if peri_clk_vif; // GPIO Pads interface virtual pins_if #(NUM_GPIOS) gpio_vif; diff --git a/hw/top_chip/dv/tb/tb.sv b/hw/top_chip/dv/tb/tb.sv index a0fac5280..8b53666dd 100644 --- a/hw/top_chip/dv/tb/tb.sv +++ b/hw/top_chip/dv/tb/tb.sv @@ -24,8 +24,6 @@ module tb; // ------ Signals ------ wire clk; wire rst_n; - wire peri_clk; - wire peri_rst_n; // GPIO connections wire [NUM_GPIOS-1:0] gpio_pads; // A wire connected to bidirectional pads in pins_if @@ -37,7 +35,6 @@ module tb; // ------ Interfaces ------ clk_rst_if sys_clk_if(.clk(clk), .rst_n(rst_n)); - clk_rst_if peri_clk_if(.clk(peri_clk), .rst_n(peri_rst_n)); uart_if uart_if(); pins_if #(NUM_GPIOS) gpio_pins_if (.pins(gpio_pads)); @@ -226,10 +223,8 @@ module tb; // Start clock and reset generators sys_clk_if.set_active(); - peri_clk_if.set_active(); uvm_config_db#(virtual clk_rst_if)::set(null, "*", "sys_clk_if", sys_clk_if); - uvm_config_db#(virtual clk_rst_if)::set(null, "*", "peri_clk_if", peri_clk_if); uvm_config_db#(virtual uart_if)::set(null, "*.env.m_uart_agent*", "vif", uart_if); uvm_config_db#(virtual pins_if #(NUM_GPIOS))::set(null, "*.env", "gpio_vif", gpio_pins_if); From bef33803616f3dbea345de58cb0997f02b17c4f7 Mon Sep 17 00:00:00 2001 From: Kinza Qamar Date: Tue, 28 Apr 2026 17:46:59 +0100 Subject: [PATCH 2/2] [chip, I2C, dv] Make sram_axi_sim use the right clock and reset Signed-off-by: Kinza Qamar --- hw/top_chip/dv/tb/tb.sv | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/top_chip/dv/tb/tb.sv b/hw/top_chip/dv/tb/tb.sv index 8b53666dd..6d21a0e26 100644 --- a/hw/top_chip/dv/tb/tb.sv +++ b/hw/top_chip/dv/tb/tb.sv @@ -102,16 +102,24 @@ module tb; end // Signals to connect the sink + logic sim_sram_clk; + logic sim_sram_rst; top_pkg::axi_req_t sim_sram_cpu_req; top_pkg::axi_resp_t sim_sram_cpu_resp; top_pkg::axi_req_t sim_sram_xbar_req; top_pkg::axi_resp_t sim_sram_xbar_resp; + // CVA6 and Xbar uses clk_main_infra from clock manager and their request and response ports are + // interfaced in sim_sram_axi_sink module. Thus, use the same clock and reset as them to stay in + // sync. + assign sim_sram_clk = dut.clkmgr_clocks.clk_main_infra; + assign sim_sram_rst = dut.rstmgr_resets.rst_main_n[rstmgr_pkg::Domain0Sel]; + // Instantiate the AXI sink to intercept the AXI traffic within the simulation memory range // to provide a dedicated channel for SW-to-DV communication. sim_sram_axi_sink u_sim_sram ( - .clk_i (clk ), - .rst_ni (rst_n ), + .clk_i (sim_sram_clk ), + .rst_ni (sim_sram_rst ), .cpu_req_i (sim_sram_cpu_req ), .cpu_resp_o (sim_sram_cpu_resp ), .xbar_req_o (sim_sram_xbar_req ),