diff --git a/docs/index.rst b/docs/index.rst
index f786f8b..541d85e 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -8,8 +8,8 @@ Core Library
    :maxdepth: 1
 
    modules/src/CVL
-   modules/src/Vector
-   modules/src/VectorRef
+   modules/src/CVL/Vector
+   modules/src/CVL/VectorRef
 
 Intrinsics
 **********
@@ -19,7 +19,7 @@ CVL implements all of the higher level vector operations using a lower level lib
 .. toctree::
    :maxdepth: 1
 
-   modules/src/Intrin
+   modules/src/CVL/Intrin
 
 Internal Intrinsics
 ~~~~~~~~~~~~~~~~~~~
@@ -29,10 +29,10 @@ These modules are the internal implementation types used by the intrinsics. They
 .. toctree::
    :maxdepth: 1
 
-   modules/src/IntrinX86_128
-   modules/src/IntrinX86_256
-   modules/src/IntrinArm64_128
-   modules/src/IntrinArm64_256
+   modules/src/CVL/IntrinX86_128
+   modules/src/CVL/IntrinX86_256
+   modules/src/CVL/IntrinArm64_128
+   modules/src/CVL/IntrinArm64_256
 
 SLEEF
 ~~~~~
@@ -43,7 +43,7 @@ See https://sleef.org/ for more information.
 .. toctree::
    :maxdepth: 1
 
-   modules/src/SLEEF
+   modules/src/CVL/SLEEF
 
 
 Utilities
@@ -52,7 +52,7 @@ Utilities
 .. toctree::
    :maxdepth: 1
 
-   modules/src/Arch
+   modules/src/CVL/Arch
 
 
 Indices and tables
diff --git a/lint/OperatorsUpToDate.sh b/lint/OperatorsUpToDate.sh
index 4dbb088..4595bf0 100755
--- a/lint/OperatorsUpToDate.sh
+++ b/lint/OperatorsUpToDate.sh
@@ -3,8 +3,8 @@
 PROJECT_DIR=$(cd $(dirname $0); cd ..; pwd)
 set -e
 
-# rebuild operators from Vectors.chpl, make sure it matches src/Vector/Operators.chpl
+# rebuild operators from Vectors.chpl, make sure it matches src/CVL/Vector/Operators.chpl
 TEMP=$(mktemp -d)
-(set -x && $PROJECT_DIR/util/generate_ops.py --filename $PROJECT_DIR/src/Vector.chpl --output $TEMP/Operators.chpl)
-(set -x && diff -u $PROJECT_DIR/src/Vector/Operators.chpl $TEMP/Operators.chpl)
+(set -x && $PROJECT_DIR/util/generate_ops.py --filename $PROJECT_DIR/src/CVL/Vector.chpl --output $TEMP/Operators.chpl)
+(set -x && diff -u $PROJECT_DIR/src/CVL/Vector/Operators.chpl $TEMP/Operators.chpl)
 (set -x && rm -rf $TEMP)
diff --git a/src/CVL.chpl b/src/CVL.chpl
index 64e1638..d4c1856 100644
--- a/src/CVL.chpl
+++ b/src/CVL.chpl
@@ -1,5 +1,18 @@
 module CVL {
   config param implementationWarnings = true;
+  // public
+  include module Vector;
+  include module VectorRef;
+
+  // helpers
+  include module Arch;
+  include module Intrin;
+  include module IntrinArm64_128;
+  include module IntrinArm64_256;
+  include module IntrinX86_128;
+  include module IntrinX86_256;
+  include module SLEEF;
+
   public use Vector;
   public use VectorRef;
 }
diff --git a/src/Arch.chpl b/src/CVL/Arch.chpl
similarity index 100%
rename from src/Arch.chpl
rename to src/CVL/Arch.chpl
diff --git a/src/Intrin.chpl b/src/CVL/Intrin.chpl
similarity index 99%
rename from src/Intrin.chpl
rename to src/CVL/Intrin.chpl
index 121375a..6d35073 100644
--- a/src/Intrin.chpl
+++ b/src/CVL/Intrin.chpl
@@ -1,12 +1,12 @@
 module Intrin {
   use CTypes only c_ptr, c_ptrConst, c_int;
-  use Arch only isX8664, isArm64;
+  use super.Arch only isX8664, isArm64;
 
   proc vectorType(type eltType, param numElts: int) type do
     return implType(eltType, numElts).vecType;
   proc implType(type eltType, param numElts: int) type {
     if isX8664() && numBits(eltType) * numElts == 128 {
-      use IntrinX86_128;
+      use super.IntrinX86_128;
       if eltType == real(32)      then return x8664_32x4r;
       else if eltType == real(64) then return x8664_64x2r;
       else if eltType == int(8)   then return x8664_8x16i;
@@ -16,7 +16,7 @@ module Intrin {
       else compilerError("Unsupported vector type");
 
     } else if isX8664() && numBits(eltType) * numElts == 256 {
-      use IntrinX86_256;
+      use super.IntrinX86_256;
       if eltType == real(32)      then return x8664_32x8r;
       else if eltType == real(64) then return x8664_64x4r;
       else if eltType == int(8)   then return x8664_8x32i;
@@ -26,7 +26,7 @@ module Intrin {
       else compilerError("Unsupported vector type");
 
     } else if isArm64() && numBits(eltType) * numElts == 128 {
-      use IntrinArm64_128;
+      use super.IntrinArm64_128;
       if eltType == real(32)      then return arm64_32x4r;
       else if eltType == real(64) then return arm64_64x2r;
       else if eltType == int(8)   then return arm64_8x16i;
@@ -36,7 +36,7 @@ module Intrin {
       else compilerError("Unsupported vector type");
 
     } else if isArm64() && numBits(eltType) * numElts == 256 {
-      use IntrinArm64_256;
+      use super.IntrinArm64_256;
       if eltType == real(32)      then return arm64_32x8r;
       else if eltType == real(64) then return arm64_64x4r;
       else if eltType == int(8)   then return arm64_8x32i;
diff --git a/src/IntrinArm64_128.chpl b/src/CVL/IntrinArm64_128.chpl
similarity index 99%
rename from src/IntrinArm64_128.chpl
rename to src/CVL/IntrinArm64_128.chpl
index 298f004..9269f5e 100644
--- a/src/IntrinArm64_128.chpl
+++ b/src/CVL/IntrinArm64_128.chpl
@@ -1,7 +1,7 @@
 @chplcheck.ignore("PascalCaseModules")
 module IntrinArm64_128 {
   use CTypes only c_ptr, c_ptrConst, c_int;
-  use Arch only isArm64;
+  use super.Arch only isArm64;
   use Reflection only canResolveTypeMethod, getRoutineName;
   if isArm64() {
     require "arm_neon.h";
diff --git a/src/IntrinArm64_128/wrapper-arm64-128-int16.h b/src/CVL/IntrinArm64_128/wrapper-arm64-128-int16.h
similarity index 100%
rename from src/IntrinArm64_128/wrapper-arm64-128-int16.h
rename to src/CVL/IntrinArm64_128/wrapper-arm64-128-int16.h
diff --git a/src/IntrinArm64_128/wrapper-arm64-128-int32.h b/src/CVL/IntrinArm64_128/wrapper-arm64-128-int32.h
similarity index 100%
rename from src/IntrinArm64_128/wrapper-arm64-128-int32.h
rename to src/CVL/IntrinArm64_128/wrapper-arm64-128-int32.h
diff --git a/src/IntrinArm64_128/wrapper-arm64-128-int64.h b/src/CVL/IntrinArm64_128/wrapper-arm64-128-int64.h
similarity index 100%
rename from src/IntrinArm64_128/wrapper-arm64-128-int64.h
rename to src/CVL/IntrinArm64_128/wrapper-arm64-128-int64.h
diff --git a/src/IntrinArm64_128/wrapper-arm64-128-int8.h b/src/CVL/IntrinArm64_128/wrapper-arm64-128-int8.h
similarity index 100%
rename from src/IntrinArm64_128/wrapper-arm64-128-int8.h
rename to src/CVL/IntrinArm64_128/wrapper-arm64-128-int8.h
diff --git a/src/IntrinArm64_128/wrapper-arm64-128-real32.h b/src/CVL/IntrinArm64_128/wrapper-arm64-128-real32.h
similarity index 100%
rename from src/IntrinArm64_128/wrapper-arm64-128-real32.h
rename to src/CVL/IntrinArm64_128/wrapper-arm64-128-real32.h
diff --git a/src/IntrinArm64_128/wrapper-arm64-128-real64.h b/src/CVL/IntrinArm64_128/wrapper-arm64-128-real64.h
similarity index 100%
rename from src/IntrinArm64_128/wrapper-arm64-128-real64.h
rename to src/CVL/IntrinArm64_128/wrapper-arm64-128-real64.h
diff --git a/src/IntrinArm64_128/wrapper-arm64-128.h b/src/CVL/IntrinArm64_128/wrapper-arm64-128.h
similarity index 100%
rename from src/IntrinArm64_128/wrapper-arm64-128.h
rename to src/CVL/IntrinArm64_128/wrapper-arm64-128.h
diff --git a/src/IntrinArm64_256.chpl b/src/CVL/IntrinArm64_256.chpl
similarity index 99%
rename from src/IntrinArm64_256.chpl
rename to src/CVL/IntrinArm64_256.chpl
index d1c8965..13eb652 100644
--- a/src/IntrinArm64_256.chpl
+++ b/src/CVL/IntrinArm64_256.chpl
@@ -2,7 +2,7 @@
 /* There is no 256 for neon, this emulates it */
 @chplcheck.ignore("PascalCaseModules")
 module IntrinArm64_256 {
-  use IntrinArm64_128 only numBits, vecTypeStr;
+  use super.IntrinArm64_128 only numBits, vecTypeStr;
   use CTypes only c_ptr, c_ptrConst, c_int;
   use Reflection only getRoutineName;
 
diff --git a/src/IntrinX86_128.chpl b/src/CVL/IntrinX86_128.chpl
similarity index 99%
rename from src/IntrinX86_128.chpl
rename to src/CVL/IntrinX86_128.chpl
index 6db542a..9865e1d 100644
--- a/src/IntrinX86_128.chpl
+++ b/src/CVL/IntrinX86_128.chpl
@@ -2,7 +2,7 @@
 module IntrinX86_128 {
   use CTypes only c_ptr, c_ptrConst, c_int;
   use Reflection only canResolveTypeMethod, getRoutineName;
-  use Arch only isX8664;
+  use super.Arch only isX8664;
   if isX8664() {
     require "x86intrin.h";
     require "IntrinX86_128/wrapper-x86-128.h";
diff --git a/src/IntrinX86_128/wrapper-x86-128-int16.h b/src/CVL/IntrinX86_128/wrapper-x86-128-int16.h
similarity index 100%
rename from src/IntrinX86_128/wrapper-x86-128-int16.h
rename to src/CVL/IntrinX86_128/wrapper-x86-128-int16.h
diff --git a/src/IntrinX86_128/wrapper-x86-128-int32.h b/src/CVL/IntrinX86_128/wrapper-x86-128-int32.h
similarity index 100%
rename from src/IntrinX86_128/wrapper-x86-128-int32.h
rename to src/CVL/IntrinX86_128/wrapper-x86-128-int32.h
diff --git a/src/IntrinX86_128/wrapper-x86-128-int64.h b/src/CVL/IntrinX86_128/wrapper-x86-128-int64.h
similarity index 100%
rename from src/IntrinX86_128/wrapper-x86-128-int64.h
rename to src/CVL/IntrinX86_128/wrapper-x86-128-int64.h
diff --git a/src/IntrinX86_128/wrapper-x86-128-int8.h b/src/CVL/IntrinX86_128/wrapper-x86-128-int8.h
similarity index 100%
rename from src/IntrinX86_128/wrapper-x86-128-int8.h
rename to src/CVL/IntrinX86_128/wrapper-x86-128-int8.h
diff --git a/src/IntrinX86_128/wrapper-x86-128-real32.h b/src/CVL/IntrinX86_128/wrapper-x86-128-real32.h
similarity index 100%
rename from src/IntrinX86_128/wrapper-x86-128-real32.h
rename to src/CVL/IntrinX86_128/wrapper-x86-128-real32.h
diff --git a/src/IntrinX86_128/wrapper-x86-128-real64.h b/src/CVL/IntrinX86_128/wrapper-x86-128-real64.h
similarity index 100%
rename from src/IntrinX86_128/wrapper-x86-128-real64.h
rename to src/CVL/IntrinX86_128/wrapper-x86-128-real64.h
diff --git a/src/IntrinX86_128/wrapper-x86-128.h b/src/CVL/IntrinX86_128/wrapper-x86-128.h
similarity index 100%
rename from src/IntrinX86_128/wrapper-x86-128.h
rename to src/CVL/IntrinX86_128/wrapper-x86-128.h
diff --git a/src/IntrinX86_128/wrapper-x86-fp-compare.h b/src/CVL/IntrinX86_128/wrapper-x86-fp-compare.h
similarity index 100%
rename from src/IntrinX86_128/wrapper-x86-fp-compare.h
rename to src/CVL/IntrinX86_128/wrapper-x86-fp-compare.h
diff --git a/src/IntrinX86_128/wrapper-x86-gathers.h b/src/CVL/IntrinX86_128/wrapper-x86-gathers.h
similarity index 100%
rename from src/IntrinX86_128/wrapper-x86-gathers.h
rename to src/CVL/IntrinX86_128/wrapper-x86-gathers.h
diff --git a/src/IntrinX86_256.chpl b/src/CVL/IntrinX86_256.chpl
similarity index 99%
rename from src/IntrinX86_256.chpl
rename to src/CVL/IntrinX86_256.chpl
index f37e96e..1ae1426 100644
--- a/src/IntrinX86_256.chpl
+++ b/src/CVL/IntrinX86_256.chpl
@@ -1,6 +1,6 @@
 @chplcheck.ignore("PascalCaseModules")
 module IntrinX86_256 {
-  use IntrinX86_128 only doSimpleOp, numBits, x8664_NxM,
+  use super.IntrinX86_128 only doSimpleOp, numBits, x8664_NxM,
                          vec32x4r, vec64x2r,
                          vec8x16i, vec16x8i, vec32x4i, vec64x2i,
                          vec8x16u, vec16x8u, vec32x4u, vec64x2u,
@@ -10,7 +10,7 @@ module IntrinX86_256 {
 
   use CTypes only c_ptr, c_ptrConst;
   use Reflection only canResolveTypeMethod;
-  use Arch only isX8664;
+  use super.Arch only isX8664;
   if isX8664() {
     require "x86intrin.h";
     require "IntrinX86_256/wrapper-x86-256.h";
diff --git a/src/IntrinX86_256/wrapper-x86-256-int16.h b/src/CVL/IntrinX86_256/wrapper-x86-256-int16.h
similarity index 100%
rename from src/IntrinX86_256/wrapper-x86-256-int16.h
rename to src/CVL/IntrinX86_256/wrapper-x86-256-int16.h
diff --git a/src/IntrinX86_256/wrapper-x86-256-int32.h b/src/CVL/IntrinX86_256/wrapper-x86-256-int32.h
similarity index 100%
rename from src/IntrinX86_256/wrapper-x86-256-int32.h
rename to src/CVL/IntrinX86_256/wrapper-x86-256-int32.h
diff --git a/src/IntrinX86_256/wrapper-x86-256-int64.h b/src/CVL/IntrinX86_256/wrapper-x86-256-int64.h
similarity index 100%
rename from src/IntrinX86_256/wrapper-x86-256-int64.h
rename to src/CVL/IntrinX86_256/wrapper-x86-256-int64.h
diff --git a/src/IntrinX86_256/wrapper-x86-256-int8.h b/src/CVL/IntrinX86_256/wrapper-x86-256-int8.h
similarity index 100%
rename from src/IntrinX86_256/wrapper-x86-256-int8.h
rename to src/CVL/IntrinX86_256/wrapper-x86-256-int8.h
diff --git a/src/IntrinX86_256/wrapper-x86-256-real32.h b/src/CVL/IntrinX86_256/wrapper-x86-256-real32.h
similarity index 100%
rename from src/IntrinX86_256/wrapper-x86-256-real32.h
rename to src/CVL/IntrinX86_256/wrapper-x86-256-real32.h
diff --git a/src/IntrinX86_256/wrapper-x86-256-real64.h b/src/CVL/IntrinX86_256/wrapper-x86-256-real64.h
similarity index 100%
rename from src/IntrinX86_256/wrapper-x86-256-real64.h
rename to src/CVL/IntrinX86_256/wrapper-x86-256-real64.h
diff --git a/src/IntrinX86_256/wrapper-x86-256.h b/src/CVL/IntrinX86_256/wrapper-x86-256.h
similarity index 100%
rename from src/IntrinX86_256/wrapper-x86-256.h
rename to src/CVL/IntrinX86_256/wrapper-x86-256.h
diff --git a/src/SLEEF.chpl b/src/CVL/SLEEF.chpl
similarity index 91%
rename from src/SLEEF.chpl
rename to src/CVL/SLEEF.chpl
index f91ffaf..354fd0f 100644
--- a/src/SLEEF.chpl
+++ b/src/CVL/SLEEF.chpl
@@ -6,8 +6,8 @@ module SLEEF {
     require SLEEF_INSTALL + "/lib/libsleef.a";
   }
 
-  use Intrin only implType, vectorType;
-  use Arch only isX8664, isArm64;
+  use super.Intrin only implType, vectorType;
+  use super.Arch only isX8664, isArm64;
 
 
   inline proc doSimpleOp(
@@ -21,7 +21,7 @@ module SLEEF {
     proc getNumLanes() param : int {
       param numLanes = impl.vecType.numBits / numBits(impl.laneType);
       if isArm64() {
-        import IntrinArm64_256.vecPair;
+        import super.IntrinArm64_256.vecPair;
         if isSubtype(impl.vecType, vecPair) then return numLanes / 2;
       }
       return numLanes;
@@ -29,7 +29,7 @@ module SLEEF {
     param funcName = "Sleef_" + name + suffix + getNumLanes():string + "_u10";
 
     if isArm64() {
-      import IntrinArm64_256.vecPair;
+      import super.IntrinArm64_256.vecPair;
       if isSubtype(impl.vecType, vecPair) {
         pragma "fn synchronization free"
         extern funcName proc func(x: impl.vecType.vt): impl.vecType.vt;
diff --git a/src/Vector.chpl b/src/CVL/Vector.chpl
similarity index 99%
rename from src/Vector.chpl
rename to src/CVL/Vector.chpl
index 743dc03..0c5d6d8 100644
--- a/src/Vector.chpl
+++ b/src/CVL/Vector.chpl
@@ -2,8 +2,8 @@ module Vector {
   use CTypes only c_ptr, c_ptrConst,
                   c_ptrTo, c_ptrToConst,
                   c_addrOf, c_addrOfConst, c_int;
-  import Intrin;
-  use VectorRef only vectorRef;
+  import super.Intrin;
+  use super.VectorRef only vectorRef;
 
   proc numBits(type t) param: int where isSubtype(t, vector) do
     return numBits(t.eltType) * t.numElts;
@@ -872,7 +872,7 @@ module Vector {
       compilerError(
         "sin is only defined for real types, not " + eltType:string);
 
-    import SLEEF.sleef;
+    import super.SLEEF.sleef;
     var result: x.type;
     result.data = sleef.sin(eltType, numElts, x.data);
     return result;
@@ -883,7 +883,7 @@ module Vector {
       compilerError(
         "cos is only defined for real types, not " + eltType:string);
 
-    import SLEEF.sleef;
+    import super.SLEEF.sleef;
     var result: x.type;
     result.data = sleef.cos(eltType, numElts, x.data);
     return result;
@@ -894,7 +894,7 @@ module Vector {
       compilerError(
         "tan is only defined for real types, not " + eltType:string);
 
-    import SLEEF.sleef;
+    import super.SLEEF.sleef;
     var result: x.type;
     result.data = sleef.tan(eltType, numElts, x.data);
     return result;
@@ -905,7 +905,7 @@ module Vector {
       compilerError(
         "asin is only defined for real types, not " + eltType:string);
 
-    import SLEEF.sleef;
+    import super.SLEEF.sleef;
     var result: x.type;
     result.data = sleef.asin(eltType, numElts, x.data);
     return result;
@@ -916,7 +916,7 @@ module Vector {
       compilerError(
         "acos is only defined for real types, not " + eltType:string);
 
-    import SLEEF.sleef;
+    import super.SLEEF.sleef;
     var result: x.type;
     result.data = sleef.acos(eltType, numElts, x.data);
     return result;
@@ -927,7 +927,7 @@ module Vector {
       compilerError(
         "atan is only defined for real types, not " + eltType:string);
 
-    import SLEEF.sleef;
+    import super.SLEEF.sleef;
     var result: x.type;
     result.data = sleef.atan(eltType, numElts, x.data);
     return result;
diff --git a/src/Vector/Operators.chpl b/src/CVL/Vector/Operators.chpl
similarity index 99%
rename from src/Vector/Operators.chpl
rename to src/CVL/Vector/Operators.chpl
index 561a4ca..3654999 100644
--- a/src/Vector/Operators.chpl
+++ b/src/CVL/Vector/Operators.chpl
@@ -3,8 +3,8 @@
 // Autogenerated by generate_ops.py: DO NOT EDIT
 //
 module Operators {
-  use Vector only vector;
-  import Intrin;
+  use super.super.Vector only vector;
+  import super.Intrin;
 
   /*
     Implements ``VECTOR + VECTOR``
diff --git a/src/VectorRef.chpl b/src/CVL/VectorRef.chpl
similarity index 99%
rename from src/VectorRef.chpl
rename to src/CVL/VectorRef.chpl
index 139d55a..5f4a299 100644
--- a/src/VectorRef.chpl
+++ b/src/CVL/VectorRef.chpl
@@ -1,6 +1,6 @@
 module VectorRef {
 
-  use Vector only vector;
+  use super.Vector only vector;
   use CTypes only c_ptr, c_ptrConst, c_ptrTo, c_ptrToConst;
 
   /* a transparent record that iterators can yield,
diff --git a/test/TestHelpers.chpl b/test/TestHelpers.chpl
index 948a94f..b603158 100644
--- a/test/TestHelpers.chpl
+++ b/test/TestHelpers.chpl
@@ -103,7 +103,7 @@ proc toHex(tup, param filled = false) where isTuple(tup) {
   }
   return res;
 }
-import Vector.vector;
+import CVL.vector;
 proc toHex(x: vector(?), param filled = false) {
   return toHex(x.toTuple(), filled=filled);
 }
diff --git a/util/generate_ops.py b/util/generate_ops.py
index 53abf48..6c7df67 100755
--- a/util/generate_ops.py
+++ b/util/generate_ops.py
@@ -348,8 +348,8 @@ def parse(self) -> List[Expression]:
 // Autogenerated by generate_ops.py: DO NOT EDIT
 //
 module @@{mod_name} {
-  use Vector only vector;
-  import Intrin;
+  use super.super.Vector only vector;
+  import super.Intrin;
 
   @@{contents}
 }