diff --git a/src/main/scala/Difftest.scala b/src/main/scala/Difftest.scala
index 20d9d8d57..1978829d0 100644
--- a/src/main/scala/Difftest.scala
+++ b/src/main/scala/Difftest.scala
@@ -546,6 +546,8 @@ object DifftestModule {
   private val nameExcludes = ListBuffer.empty[String]
   private val cmdConfigs = ListBuffer.empty[String]
 
+  def isFPGA: Boolean = Gateway.isFPGA
+
   // Some FIRTOOL options are customized for DiffTest
   def parseArgs(args: Array[String]): (Array[String], Seq[FirtoolOption]) = {
     cmdConfigs ++= args
diff --git a/src/main/scala/Gateway.scala b/src/main/scala/Gateway.scala
index 37baf3f94..b77e37267 100644
--- a/src/main/scala/Gateway.scala
+++ b/src/main/scala/Gateway.scala
@@ -156,6 +156,8 @@ object Gateway {
   private val instanceWithDelay = ListBuffer.empty[(DifftestBundle, Int)]
   private var config = GatewayConfig()
 
+  def isFPGA: Boolean = config.isFPGA
+
   def setConfig(cfg: String): Unit = {
     cfg.foreach {
       case 'E' => config = config.copy(hasGlobalEnable = true)
diff --git a/src/main/scala/SimTop.scala b/src/main/scala/SimTop.scala
index 62acc7593..495d59822 100644
--- a/src/main/scala/SimTop.scala
+++ b/src/main/scala/SimTop.scala
@@ -208,12 +208,6 @@ class SimTop[T <: RawModule with HasDiffTestInterfaces](cpuGen: => T, modPrefix:
     }
   }
 
-  if (gateway.fpgaIO.isEmpty) {
-    cpu.difftestMemIO.foreach { case DifftestMemIO(cpuRecord, memRecord) =>
-      require(memRecord.isDefined, "Non-FPGA difftest memory requires a memory AXI sink")
-      AXI4Bundle.connectRecord(memRecord.get, cpuRecord)
-    }
-  }
   cpu.dutReset := (reset.asBool || fpgaHostReset).asTypeOf(cpu.dutReset)
   cpu.connectTopIOs(difftest)
   cpu.dutIOs.foreach { case (name, gen) =>